View ADM1034ARQZ-REEL_762901.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ADM1034 Thermal Monitor and Fan Speed (RPM) Controller
The ADM1034 is a dual-channel remote- and local-temperature sensor and fan controller. The remote channels monitor the temperature of two remote thermal diodes, which may be discrete 2N3904/6s or may be located on a microprocessor die. The device also monitors its own ambient temperature. The ADM1034 can monitor and control the speed of two cooling fans. The user can program a target fan speed, or else use the look-up table to input a temperature-to-fan speed profile. The look-up table can be configured to run the fans at discrete speeds (discrete mode) or to ramp the fan speed with temperature (linear mode). The ADM1034 communicates over a 2-wire SMBus 2.0 interface. An 8-level LOCATION input allows the user to choose between SMBus 1.1 and SMBus 2.0. An ALERT output indicates error conditions. The THERM I/O signals overtemperature as an output and times THERM assertions as an input. Pin 8 can be configured as a reference for the THERM (PROCHOT) input.
FEATURES http://onsemi.com
MARKING DIAGRAM
QSOP-16 CASE 492
1034A RQZ #YYWW
# = Pb-Free Package YYWW = Date Code
* * * * * * * * * * * * * * * * * * * * * * *
1 Local and 2 Remote Temperature Channels 1C Accuracy on Local and Remote Channels Automatic Remote Temperature Channels, Up to 1 kW Fast (Up to 64 Measurements per Second) SMBus 2.0, 1.1, and 1.0 Compliant SMBus Address Input/LOCATION Input to UDID Programmable Over/Undertemperature Limits Programmable Fault Queue SMBusALERT Output Fail-Safe Overtemperature Comparator Output Fan Speed (RPM) Controller Look-Up Table for Temperature-to-Fan Speed Control Linear and Discrete Options for Look-Up Table FAN_FAULT Output THERM Input, Used to Time PROCHOT Assertions REF Input, Used as Reference for THERM (PROCHOT) 3.0 V to 5.5 V Supply Small 16-Lead QSOP Package This is a Pb-Free Device
PIN ASSIGNMENT
DRIVE1 TACH1 DRIVE2 TACH2 GND VCC THERM FAN_FAULT/REF
1 2 3 4 5 6 7 8 16 15 14
ADM1034
13 12 11 10 9
SCL SDA ALERT LOCATION D2+ D2- D1+ D1-
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 38 of this data sheet.
APPLICATIONS
Desktop and Notebook PCs Embedded Systems Telecommunications Equipment LCD Projectors
(c) Semiconductor Components Industries, LLC, 2009
July, 2009 - Rev. 3
1
Publication Order Number: ADM1034/D
ADM1034
VCC
6
ADM1034
SMBUS ADDRESS SERIAL BUS INTERFACE ADDRESS POINTER REGISTER ALERT STATUS REGISTER THERM MASK REGISTERS FAULT QUEUE
16 15
SCL SDA
MANUAL FAN SPEED CONTROL REGISTERS
8
FAN_FAULT
TEMPERATURE-TO- FAN-SPEED LOOK-UP TABLE
14 ALERT 7
THERM
DRIVE1 1 DRIVE2 3
FAN SPEED CONTROLLER
FAN RESPONSE
LIMIT COMPARATOR
TACH1 2 TACH2
4
TACH SIGNAL CONDITIONING
FAN SPEED COUNTER
VALUE AND LIMIT REGISTERS FAULT QUEUE HYSTERESIS REGISTERS
THERM PERCENT TIMER
REF 8 LOCATION 13 D1-
9
D1+ 10 D2- 11 D2+ 12
SRC BLOCK
ANALOG MULTIPLEXER
ADC
OFFSET REGISTERS CONVERSION RATE REGISTER CONFIGURATION REGISTERS
5
BAND GAP REFERENCE BAND GAP TEMPERATURE SENSOR
GND
Figure 1. Functional Block Diagram
http://onsemi.com
2
ADM1034
ABSOLUTE MAXIMUM RATINGS
Parameter Positive Supply Voltage (VCC) Voltage on Any Input or Output Pin except FAN_FAULT and LOCATION Voltage on FAN_FAULT (Note 1) Voltage on LOCATION Input Current at Any Pin Maximum Junction Temperature (TJ max) Storage Temperature Range Lead Temperature, Soldering (10 s) IR Reflow Peak Temperature Rating -0.3, +6.5 -0.3 to VDD +6.5 VCC VCC + 0.3 20 150 -65 to +150 300 220 V mA C C C C Unit V V
ESD Rating - All Pins 1500 V 1. During powerup the voltage on FAN_FAULT should not be higher than VCC. Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.
THERMAL CHARACTERISTICS
Parameter 16-Lead QSOP Package Rating qJA = 150C/W, qJC = 39C/W
PIN ASSIGNMENT
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Mnemonic DRIVE1 TACH1 DRIVE2 TACH2 GND VCC THERM FAN_FAULT/REF D1- D1+ D2- D2+ LOCATION ALERT SDA SCL Description DRIVE1 Pin Drives Fan 1. Open-drain output. Requires a pullup resistor. Fan 1 Fan Speed Measurement Input. Connects to the fan's TACH output to measure the fan speed. DRIVE2 Pin Drives Fan 2. Open-drain output. Requires a pullup resistor. Fan 2 Fan Speed Measurement Input. Connects to the fan's TACH output to measure the fan speed. Ground for Analog and Digital Circuitry. Power. Can be powered by 3.3 V standby power if monitoring in low power states is required. Can be configured as an overtemperature interrupt output, or as an input (to monitor PROCHOT output of an INTEL CPU). A timer measures assertion times on the THERM pin (either input or output). FAN_FAULT: Open-Drain Output. Asserted low when one or both fans stall. Requires a pullup resistor to VCC. REF: Analog Input Reference for the THERM Input. Cathode Connection for the First Thermal Diode or Diode-Connected Transistor. Anode Connection for the First Thermal Diode or Diode-Connected Transistor. Cathode Connection for the Second Thermal Diode or Diode-Connected Transistor. Anode Connection for the Second Thermal Diode or Diode-Connected Transistor. 8-Level Analog Input. Used to determine the correct SMBus version and the SMBus address (in fixed and discoverable mode) and to set the LLL bits in the UDID (in ARP-capable mode). Open-Drain Output. SMBusALERT pin. Alerts the system in the case of out-of-limit events, such as over temperature. Can be configured as sticky SMBus mode or comparator mode. Serial Bus Bidirectional Data. Connects to the SMBus master's data line. Requires pullup resistor if not provided elsewhere in the system. Serial SMBus Clock Input. Connects to the SMBus master's clock line. Requires pullup resistor if not already provided in the system.
http://onsemi.com
3
ADM1034
ELECTRICAL CHARACTERISTICS (TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted. (Note 1)
Parameter Power Supply Supply Voltage, VCC (Note 2) Supply Current, ICC Undervoltage Lockout Threshold Power-On Reset Threshold Temperature-to-Digital Converter Internal Sensor Accuracy Resolution External Diode Sensor Accuracy -40C TD +100C; TA = +40C -40C TD +100C; +20C TA +60C -40C TD +100C; -40C TA +100C High level Mid level Low level +20C TA +60C -40C TA +100C 1.0 0.03125 0.5 1.0 0.03125 87 33 5.5 1000 1.0 Averaging enabled Averaging enabled Averaging enabled IOUT = -6.0 mA; VCC = +3 V VOUT = VCC; VCC = 3 V -VIN = VCC VIN = 0 7.0 2.0 -0.3 500 IOUT = -6.0 mA; VCC VOUT = VCC 2.1 0.8 500 80 125 160 0.1 0.4 1.0 5.5 +0.8 -1.0 1.0 0.1 11 32 75 0.4 1.0 1.0 1.25 2.5 2.0 2.5 C C C 1.0 Interface inactive, ADC active Standby mode 2.5 2.4 3.0 3.30 3.6 3.0 900 V mA mA V V Test Conditions / Comments Min Typ Max Unit
Resolution Remote Sensor Source Current
C mA
Series Resistance Cancellation Power Supply Sensitivity Conversion Time (Local Temperature) Conversion Time (Remote Temperature) Total Conversion Time Output Low Voltage, VOL High Level Output Leakage Current, IOH Input High Current, IIH Input Low Current, IIL Input Capacitance, CIN Digital Input Logic Levels (TACH1, TACH2) Input High Voltage, VIH Input Low Voltage, VIL Hysteresis Open-Drain Serial Data Bus Output (SDA) Output Low Voltage, VOL High Level Output Leakage Current, IOH Serial Data Bus Inputs (SCL, SDA) Input High Voltage, VIH Input Low Voltage, VIL Hysteresis Analog Inputs (Location, REF) Input Resistance
W %/V ms ms ms V mA mA mA pF V V mV p-p V mA V V mV kW
Open-Drain Digital Outputs (ALERT, THERM, FAN_FAULT, DRIVE1, DRIVE2) (Note 3)
Digital Input Leakage Current (TACH1, TACH2)
1. Typicals are at TA = 25C and represent most likely parametric norm. Standby current typ. is measured with VCC = 3.3 V. Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.1 V for a rising edge. 2. Operation at 5.5 V is guaranteed by design, not production tested. 3. Recommend use of 100 kW pullup resistors for all open-drain outputs from the ADM1034. 4. Guaranteed by design, not production tested. 5. SMBus timeout disabled by default. See the SMBus section for more information.
http://onsemi.com
4
ADM1034
ELECTRICAL CHARACTERISTICS (TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted. (Note 1)
Parameter AGTL + INPUT (THERM) Input High Level Input Low Level Tachometer Accuracy Fan Speed Measurement Accuracy SERIAL BUS TIMING (Note 4) Clock Frequency, fSCLK Glitch Immunity, tSW Bus Free Time, tBUF Start Setup Time, tSU:STA Start Hold Time, tHD:STA Stop Condition Setup Time tSU:STO SCL Low Time, tLOW SCL High Time, tHIGH SCL, SDA Rise Time, tr SCL, SDA Fall Time, tf Data Setup Time, tSU:DAT Detect Clock Low Timeout, tTIMEOUT See Figure 2 See Figure 2 See Figure 2 See Figure 2 See Figure 2 See Figure 2 See Figure 2 See Figure 2 See Figure 2 See Figure 2 See Figure 2 See Note 5 100 25 35 1.3 0.6 0.6 0.6 1.3 0.6 1000 300 50 400 kHz ns ms ms ms ms ms ms ns ns ns ms 4.0 % 0.75 x REF 0.4 V V Test Conditions / Comments Min Typ Max Unit
1. Typicals are at TA = 25C and represent most likely parametric norm. Standby current typ. is measured with VCC = 3.3 V. Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.1 V for a rising edge. 2. Operation at 5.5 V is guaranteed by design, not production tested. 3. Recommend use of 100 kW pullup resistors for all open-drain outputs from the ADM1034. 4. Guaranteed by design, not production tested. 5. SMBus timeout disabled by default. See the SMBus section for more information.
tLOW
SCL
tR
tF
tHD:STA
tHD:STA
SDA
tHD:DAT
tHIGH
tSU:DAT
tSU:STA
tSU:STO
tBUF
P S
S
P
Figure 2. Serial Bus Timing Diagram
http://onsemi.com
5
ADM1034
TYPICAL CHARACTERISTICS
40 20 TEMPERATURE ERROR (C) 0 -20 -40 -60 -80 -100 D+ TO GND D+ TO VCC TEMPERATURE ERROR (C) 0 -10 -20 -30 -40 -50 -60 -70 -80 DEV 32 (C) DEV 31 (C) DEV 33 (C)
0
10
20
30 40 50 60 70 LEAKAGE RESISTANCE (M)
80
90
100
0
2
4
6 8 CAPACITANCE (nF)
10
12
Figure 3. Temperature Error vs. PCB Track Resistance DXP to GND and VCC
100 90 80 TEMPERATURE ERROR (C) 70 60 50 40 30 20 10 0 -10 1 2 3 4 5 SERIES RESISTANCE IN D+/D LINES (k) 6 -10 0 DEV 32 DEV 31 DEV 33 TEMPERATURE ERROR (C) 20
Figure 4. Remote Temperature Error vs. D+, D- Capacitance
EXT 100mVpp EXT 250mVpp 15
10
5
0
-5
1M
2M
3M
4M
5M
6M
Figure 5. Remote Temperature Error vs. Series Resistance on D+ and D-
50 45 TEMPERATURE ERROR (C) TEMPERATURE ERROR (C) 40 35 30 25 20 15 10 5 00 0 1M 2M 3M 4M NOISE FREQUENCY (Hz) 50mV 20mV 100mV 4.0 3.5 3.0 2.5 2.0
Figure 6. Remote Temperature Error vs. Power Supply Noise Frequency
20mV 1.5 1.0 0.5
10mV 0 1M 2M 3M 4M NOISE FREQUENCY 5M 6M
5M
6M
0
Figure 7. Remote Temperature Error vs. Common-Mode Noise Frequency Coupled on D+ and D-
Figure 8. Remote Temperature Error vs. Differential Mode Noise Frequency Coupled on D+ and D-
http://onsemi.com
6
ADM1034
TYPICAL CHARACTERISTICS
1.0 USL TEMPERATURE ERROR (C) TEMPERATURE ERROR (C) 0.5
3 2
USL
1
0
0 MEAN
-0.5 MEAN
-1
-1.0
-2 LSL -1.5 -60 -3 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 ACTUAL TEMPERATURE (C) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 1 2 3 4 5 6 ACTUAL TEMPERATURE (C) 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LSL
Figure 9. Remote 1 Temperature Error vs. Actual Temperature
Figure 10. Local Temperature Error vs. Actual Temperature
430 420 410 400 DEV 33 390 380 DEV 32 370 360 DEV 31 STANDBY SUPPLY CURRENT
0.7 0.6 0.5 0.4 0.3 0.2 0.1 0
ICC (A)
1
10 FSCL (kHz)
100
1000
0
1
2 3 4 SUPPLY VOLTAGE (V)
5
6
Figure 11. Standby Supply Current vs. SCLK Frequency
Figure 12. Standby Supply Current vs. Supply Voltage
http://onsemi.com
7
ADM1034
TYPICAL CHARACTERISTICS
1200 1.55
1000
1.50
800 ICC (A)
SUPPLY CURRENT 10 100
1.45
600 DEV 31 400 DEV 33 200 DEV 32
1.40
1.35
1.30
0 0.01
0.1
1 CONVERSION RATE (Hz)
1.25 -60
-40
-20
0 20 40 TEMPERATURE (C)
60
80
100
Figure 13. Supply Current vs. Conversion Rate
Figure 14. Supply Current vs. ADM1034 Temperature
Functional Description
The ADM1034 is a local- and remote-temperature monitor and fan controller for use in a variety of applications, including microprocessor-based systems. The device accurately monitors remote and ambient temperature and uses that information to quietly control the speed of a cooling fan. Whenever one of the fans stalls, the device asserts a FAN_FAULT output. The ADM1034 features a THERM I/O. As an input, this measures assertions on the THERM pin. As an output, it asserts a low signal to indicate when the measured temperature exceeds the programmed THERM temperature. The ADM1034 communicates over an SMBus 2.0 interface. Its LOCATION input determines which version of SMBus to use, as well as the SMBus address (in fixed and discoverable mode) and the LOCATION bits in the UDID (in ARP-capable mode).
Internal Registers
the ADM1034 powers up with a fixed address, which is determined by the state of the LOCATION pin on powerup. NOTE: When using the ADM1034, Addresses 0xC2 and 0xCA should not be used by any other device on the bus.
Location Input
The LOCATION input is a resistor divider input. It has multiple functions and can specify the SMBus version (in fixed and discoverable or ARP-capable modes); the SMBus address (in fixed and discoverable mode); and the LLL bits (in UDID in ARP-capable mode). The voltage of this 8-level input is set by a potential divider. The voltage on LOCATION is sampled on powerup and digitized by the on-chip ADC to determine the LOCATION input value. Because the LOCATION input is sampled only at powerup, changes made while power is applied have no effect.
VCC R1 PIN 13 R2 GND
Table 1 gives a brief description of the ADM1034's principal internal registers. For more detailed information on the function of each register, refer to Table 31.
Serial Bus Interface
ADM1034
LOCATION
The ADM1034 communicates with the master via the 2-wire SMBus 2.0 interface. It supports two versions of SMBus 2.0, determined by the value of the LOCATION input's resistors. The first version is fully ARP-capable. This means that it supports address resolution protocol (ARP), allowing the master to dynamically address the device on powerup. It responds to ARP commands such as "Prepare to ARP." The second SMBus version, fixed and discoverable, is backwards compatible with SMBus 1.0 and 1.1. In this mode,
Figure 15. Bootstrapping the LOCATION Input SMBus 2.0 ARP-Capable Mode
In ARP-capable mode, the ADM1034 supports features such as address resolution protocol (ARP) and unique device identifier (UDID). The UDID is a 128-bit message that describes the ADM1034's capabilities to the master. The UDID also includes a vendor specific ID for functionally equivalent devices.
http://onsemi.com
8
ADM1034
VCC ARP LOCATION = 111 ARP LOCATION = 110 ARP LOCATION = 101 ARP LOCATION = 100 FD ADDRESS = 53h FD ADDRESS = 52h FD ADDRESS = 51h FD ADDRESS = 50h GND
ADM1034 1
1.5k
ADM1034 2
1k
ADM1034 3
1k
ADM1034 4
1k
ADM1034 5
1k
ADM1034 6
1k
ADM1034 7
1.5k
ADM1034 8
Figure 16. Setting Up Multiple ADM1034 Addresses in SMBus 2.0 ARP-Capable Mode
In SMBus 2.0 mode, this vendor specific ID is generated by an on-chip random number generator. This should enable two adjacent ADM1034s in the same system to powerup with a different vendor specific ID, allowing the master to identify the two separate ADM1034's and assign a different address to each. The state of the LOCATION input on powerup is also reflected in the UDID. This is useful when there is more than one ADM1034 in the system, so the master knows which one it is communicating with. The complete UDID is listed in Table 3. The SMBus 2.0 master issues both general and directed ARP commands. A general command is directed at all ARP devices. A directed command is targeted at a single device once an address has been established. The PEC byte must be used for ARP commands. (Refer to the Packet Error Checking (PEC) section.) The ADM1034 responds to the following commands: * Prepare to ARP (general) * Reset device (general and directed) * Get UDID (general and directed) * Assign address (general)
Table 1. Internal Register Descriptions
Register Configuration Conversion Rate Address Pointer Status Interrupt Mask Value and Limit Offset Description Provides control and configuration of various functions on the device. Determines the number of measurements per second completed by the ADM1034. Contains the address that selects one of the other internal registers. When writing to the ADM1034, the first byte of data is always a register address, written to the address pointer register. Provides the status of each limit comparison. Allows the option to mask ALERTs due to particular out-of-limit conditions. Stores the results of temperature and fan speed measurements, along with their limit values. Allows the local and remote temperature channel readings to be offset by a twos complement value written to them. These values are automatically added to the temperature values (or subtracted from them if negative). This allows the systems designer to optimize the system if required, by adding or subtracting up to 15.875C from a temperature reading. Contains the temperature value at which THERM is asserted and indicates the level of hysteresis. Used to program the look-up table for the fan speed-to-temperature profile. Reflects the state of the THERM input and monitors the duration of the assertion time of the signal as a percentage of a time window. The user can program the length of the time window.
THERM Limit and Hysteresis Look-Up Table THERM % On-time and THERM % Limit
Table 2. Resistor Ratios for Setting LOCATION Bits
Ideal Ratio R2/(R1 + R2) N/A 0.8125 0.6875 0.5625 0.4375 0.3125 0.1875 N/A R1 kW 0 18 22 12 15 47 82 O/C R2 W O/C 82 47 15 12 22 18 0 Actual R2/(R1 + R2) 1 0.82 0.6812 0.5556 0.4444 0.3188 0.18 0 Error % 0 +0.75 -0.63 -0.69 +0.69 +0.63 -0.75 0 SMBus Ver (Note 1) ARP ARP ARP ARP FD FD FD FD SMBus Address N/A N/A N/A N/A 0x53 0x52 0x51 0x50 UDID LLL 111 110 101 100 N/A N/A N/A N/A
1. ARP denotes ARP-capable mode, FD denotes fixed and discoverable mode.
http://onsemi.com
9
ADM1034
Table 3. UDID Values
Bit No. <127:120> <119:112> <111:96> <95:80> <79:64> <63:48> <47:32> <31:0> Name Device Capabilities Version/Revision Vendor ID Device ID Interface Subsystem Vendor ID Subsystem Device ID Vendor Specific ID Function Describes the ADM1034's capabilities (for instance, that it supports PEC and uses a random number address device). UDID version number (Version 1) and silicon revision identification Analog Devices vendor ID number, as assigned by the SBS Implementer's Forum or the PCI SIG. Device ID. Identifies the protocol layer interfaces supported by the ADM1034. This represents SMBus 2.0 as the Interface version.. Subsystem Vendor ID = 0 (subsystem fields are unsupported). Subsystem Device ID = 0 (subsystem fields are unsupported). A unique number per device. Contains LOCATION information (LL) and a 16-bit random number (x). See Table 5 for information on setting the LLL bits. Value 11000001 00001010 00010001 11010100 00010000 00110100 00000000 00000100 00000000 00000000 00000000 00000000 00000000 00000LLL xxxxxxxx xxxxxxxx
SMBus 2.0 Fixed and Discoverable Mode
The ADM1034 also supports fixed and discoverable mode, which is backwards compatible with SMBus 1.0 and 1.1. Fixed and discoverable mode supports all the same functionality as ARP-capable mode, except for assign address in which case it powers up with a fixed address and is not changed by the assign address call. The fixed address is determined by the state of the LOCATION pin on powerup.
SMBus 2.0 Read and Write Operations
The master initiates data transfer by establishing a start condition, defined as a high-to-low transition on the serial data line (SDA) while the serial clock line (SCL) remains high. This indicates that an address/data stream is to follow. All slave peripherals connected to the serial bus respond to the start condition and shift in the next 8 bits, which consist of a 7-bit address (MSB first) plus an R/W bit. This last bit determines the direction of the data transfer (whether data is written to or read from the slave device). 1. The peripheral that corresponds to the transmitted address responds by pulling the data line low during the low period before the 9th clock pulse, which is known as the acknowledge bit. All other devices on the bus remain idle while the selected device waits for data to be read from or written to it. If the R/W bit is a 0, the master writes to the slave device. If the R/W bit is a 1, the master reads from it. 2. Data is sent over the serial bus in sequences of 9 clock pulses - 8 bits of data followed by an acknowledge bit from the slave device. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, because a low-to-high transition when the clock is high may be interpreted as a stop signal. The number of data bytes that can be
transmitted over the serial bus in a single read or write operation is limited only by what the master and slave devices can handle. 3. When all data bytes have been read or written, stop conditions are established. In write mode, the master pulls the data line high during the 10th clock pulse to assert a stop condition. In read mode, the master device overrides the acknowledge bit by pulling the data line high during the low period before the 9th clock pulse. This is known as no acknowledge. The master takes the data line low during the low period before the 10th clock pulse, then high during the 10th clock pulse to assert a stop condition. It is not possible to mix read and write in one operation, because the type of operation is determined at the beginning and cannot be changed without starting a new operation. To write data to one of the device data registers or to read data from it, the address pointer register (APR) must be set so that the correct data register is addressed; then data can be written into that register or read from it. The first byte of a write operation always contains an address that is stored in the APR. If data is to be written to the device, then the write operation contains a second data byte, which is written to the register selected by the APR. As illustrated in Figure 17, the device address is sent over the bus, followed by R/W set to 0. This is followed by two data bytes. The first data byte is the address of the internal data register to be written to, which is stored in the APR. The second data byte is the data to be written to the internal data register. When reading data from a register there are two possibilities. If the ADM1034's APR value is unknown or incorrect, it must be set to the correct value before data can be read from the desired data register. To do this, perform a write to the
http://onsemi.com
10
ADM1034
ADM1034 as before, but send only the data byte containing the register. (See Figure 18.) A read operation is then performed, using the serial bus address and the R/W bit set to 1, followed by the data byte read from the data register. (See Figure 19.) However, if the APR is already at the desired address, data can be read from the corresponding data register without first writing to the APR. In this case, Figure 18 can be omitted. In Figure 17 to Figure 19, the serial bus address is determined by the state of the LOCATION pin on powerup.
9 1 9
1 SCL
SDA START BY MASTER
A6
A5
A4
A3
A2
A1
A0
R/W ACK. BY ADM1034
D7
D6
D5
D4
D3
D2
D1
D0 ACK. BY ADM1034
FRAME 1 SERIAL BUS ADDRESS BYTE 1 SCL (CONTINUED)
FRAME 2 ADDRESS POINTER REGISTER BYTE 9
SDA (CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0 ACK. BY ADM1034 STOP BY MASTER
FRAME 3 DATA BYTE
Figure 17. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register
1 SCL 9 1 9
SDA START BY MASTER
A6
A5
A4
A3
A2
A1
A0
R/W ACK. BY ADM1034
D7
D6
D5
D4
D3
D2
D1
D0 ACK. BY ADM1034 STOP BY MASTER
FRAME 1 SERIAL BUS ADDRESS BYTE
FRAME 2 ADDRESS POINTER REGISTER BYTE
Figure 18. Writing to the Address Pointer Register Only (Send Byte)
1 SCL
9
1
9
SDA START BY MASTER
A6
A5
A4
A3
A2
A1
A0
R/W ACK. BY ADM1034
D7
D6
D5
D4
D3
D2
D1
D0 NO ACK. BY STOP BY ADM1034 MASTER
FRAME 1 SERIAL BUS ADDRESS BYTE
FRAME 2 DATA BYTE FROM ADM1034
Figure 19. Reading Data from a Previously Selected Register
Register Addresses for Single/Block Byte Modes
The ADM1034 supports single byte as well as block read and write operations. The register address determines whether a single byte or multiple byte (block) operation is run. For a single byte operation, the MSB of the register address is set to 0; for a multiple byte operation, it is set to 1. The number of bytes read in a multiple byte operation is set
in the #Bytes/Block Read Register at Address 0x00. The number of bytes written to the ADM1034 is specified during the block write operation. The addresses quoted in the register map and throughout this data sheet assume single byte operation. For multiple byte operations, set the MSB of each register address to 1.
http://onsemi.com
11
ADM1034
Write Operations
The SMBus specifications define protocols for read and write operations. The ADM1034 supports send byte, write byte, and block byte SMBus write protocols. The following abbreviations are used in the diagrams: S--START P--STOP R--READ W--WRITE A--ACKNOWLEDGE A--NO ACKNOWLEDGE
Send Byte
S
SLAVE REG WA A ADDRESS ADDRESS
DATA
AP
Figure 21. Write Byte Operation Block Write
In this operation, the master device sends a single-command byte to a slave device as follows: 1. The master device asserts a start condition on SDA. 2. The master sends a 7-bit address followed by the write bit (low). 3. The addressed slave device asserts ACK on SDA. 4. The master sends the register address. 5. The slave asserts ACK on SDA. 6. The master asserts a stop condition on SDA, and the transaction ends.
S SLAVE REG WA AP ADDRESS ADDRESS
In this operation, the master device writes a block of data to a slave address as follows. A maximum of 32 bytes can be written. 1. The master asserts a start condition on SDA. 2. The master sends the 7-bit slave address followed by a write bit (low). 3. The addressed slave device asserts ACK on SDA. 4. The master sends the register address. The register address sets up the address pointer register and determines whether a block write (MSB = 1) or a byte write (MSB = 0) takes place. 5. The slave asserts ACK on SDA. 6. The master sends the byte count. 7. The slave asserts ACK on SDA. 8. The master sends N data bytes. 9. The slave asserts ACK on SDA after each byte. 10. The master asserts a stop condition on SDA to end the transaction.
S SLAVE WA ADDRESS REGISTER ADDRESS A BYTE A DATA 1 A DATA 2 A DATA N A P COUNT
Figure 20. Send Byte
The ADM1034 uses the send byte operation to write a register address to the APR for a subsequent read from the same address. (See Figure 24.) The user may be required to read data from the register immediately after setting up the address. If so, the master can assert a repeat start condition immediately after the final ACK and carry out a single byte read without asserting an intermediate stop condition.
Write Byte
Figure 22. Block Write to RAM Read Operations Receive Byte
In this operation, the master device sends a register address and one data byte to the slave device as follows: 1. The master asserts a start condition on SDA. 2. The master sends the 7-bit slave address followed by a write bit (low). 3. The addressed slave device asserts ACK on SDA. 4. The master sends the register address. The MSB of the register address should equal 0 for a write byte operation. If the MSB equals 1, a block write operation takes place. 5. The slave asserts ACK on SDA. 6. The master sends a data byte. 7. The slave asserts ACK on SDA. 8. The master asserts a stop condition on SDA to end the transaction.
This is useful when repeatedly reading a single register. The register address must be set up prior to this, with the MSB at 0 to read a single byte. In this operation, the master device receives a single byte from a slave device as follows: 1. The master device asserts a start condition on SDA. 2. The master sends the 7-bit slave address followed by the read bit (high). 3. The addressed slave device asserts ACK on SDA. 4. The master receives a data byte. 5. The master sends NO ACK on SDA. 6. The master asserts a stop condition on SDA, and the transaction ends. In the ADM1034, the receive byte protocol is used to read a single byte from a register whose address has previously been set by a send byte or write byte operation.
S SLAVE RA ADDRESS DATA AP
Figure 23. Receive Byte
http://onsemi.com
12
ADM1034
Block Read Alert Response Address (ARA)
S ALERT RESPONSE DEVICE RA AP ADDRESS ADDRESS
In this operation, the master reads a block of data from a slave device. The number of bytes to be read must be set in advance. To do this, use a write byte operation to the #Bytes/Block Read Register at Address 0x00. The register address determines whether a block-read or a read-byte operation is to be completed (set MSB to 1 to specify a block-read operation). A maximum of 32 bytes can be read. 1. The master asserts a start condition on SDA. 2. The master sends the 7-bit slave address followed by the write bit (low). 3. The addressed slave device asserts ACK on SDA. 4. The master sends the register address (MSB = 1). 5. The slave asserts ACK on SDA. 6. The master asserts a repeated start on SDA. 7. The master sends the 7-bit slave address followed by the read bit (high). 8. The slave asserts ACK on SDA. 9. The slave sends the byte count. 10. The master asserts ACK on SDA. 11. The slave sends N data bytes. 12. The master asserts ACK on SDA after each data byte. 13. The master does not acknowledge after the Nth data byte. 14. The master asserts a stop condition on SDA to end the transaction.
S SLAVE WA ADDRESS REGISTER ADDRESS AS BYTE SLAVE RA A DATA 1 A DATA N A P COUNT ADDRESS
Figure 25. ALERT Response Address
Figure 24. Block Read from RAM SMBus Timeout
When multiple devices exist on the same bus, the ARA feature allows an interrupting device to identify itself to the host. The ALERT output can be used as an interrupt output or as an SMBusALERT. One or more ALERT outputs can be connected to a common SMBusALERT line, connected to the master. If a device's ALERT line goes low, the following occurs: 1. SMBusALERT is pulled low. 2. The master initiates a receive byte operation and sends the alert response address (ARA 0001 100). This is a general call address that must not be used as a specific address. 3. The device with the low ALERT output responds to the ARA, and the master reads its device address. Once the address is known, it can be interrogated in the usual way. 4. If low ALERT output is detected in more than one device, the one with the lowest device address has priority, in accordance with normal SMBus arbitration. 5. Once the ADM1034 has responded to the ARA, it resets its ALERT output. However, if the error persists, the ALERT is re-asserted on the next monitoring cycle. Temperature Measurement System
Internal Temperature Measurement
The ADM1034 has a programmable SMBus timeout feature. When this is enabled, the SMBus typically times out after 25 ms of no activity. The timeout is disabled by default. It prevents hangups by releasing the bus after a period of inactivity. To enable the SDA timeout, set the SDA timeout bit (Bit 5) of Configuration Register 1 (Address 0x01) to 1. To enable the SCL timeout, set the SCL timeout bit (Bit 4) of Configuration Register 1 (Address 0x01) to 1.
Packet Error Checking (PEC)
The ADM1034 also supports packet error checking (PEC). This optional feature is triggered by the extra clock for the PEC byte. The PEC byte is calculated using CRC-8. The frame check sequence (FCS) conforms to CRC-8 by the following:
C(x) + x 8 ) x 2 ) x ) 1
(eq. 1)
The ADM1034 contains an on-chip band gap temperature sensor. The on-chip ADC performs conversions on the sensor's output, outputting the data in 13-bit format. The resolution of the local temperature sensor is 0.03125C. Table 4 shows the format of the temperature data MSBs. Table 5 shows the same for the LSBs. To ensure accurate readings, read the LSBs first. This locks the current LSBs and MSBs until the MSBs are read. They then start to update again. (Reading only the MSBs does not lock the registers.) Temperature updates to the look-up table take place in parallel; so fan speeds may be updated even if the MSBs are locked.
For more information, consult www.SMBus.org.
http://onsemi.com
13
ADM1034
Table 4. Temperature Data Format - (Local Temperature and Remote Temperature High Bytes)
Temperature (5C) -64C -40C -32C -2C -1C 0C 1C 2C 10C 20C 50C 75C 100C 125C 150C 191C Digital Output 0000 0000 0001 1000 0010 0000 0011 1110 0011 1111 0100 0000 0100 0001 0100 0010 0100 1010 0101 0100 0111 0010 1000 1011 1010 0100 1011 1101 1101 0110 1111 1111
2N3906
individual calibration is required to null this out. Therefore, the technique is unsuitable for mass production.
ADM1034
D+ 2N3904
ADM1034
D+
D-
D-
Figure 26. Measuring Temperature by Using Discreet Transistors
Table 5. Local and Remote Sensor Extended Resolution
Extended Resolution (5C) 0.0000 0.03125 0.0625 0.125 0.250 0.375 0.500 0.625 0.750 0.875 Temperature Low Bits 00000 00001 00010 00100 01000 01100 10000 10100 11000 11100
Temperature (C) = (MSB - 64C) + (LSB x 0.03125) Example: MSB = 0101 0100 = 84d LSB = 11100 = 28 Temperature C = (84 - 64) + (28 x 0.03125) = 20.875
Remote Temperature Measurement
The ADM1034 can measure the temperature of two external diode sensors or diode-connected transistors, which are connected to Pins 9 and 10 and Pins 11 and 12. These pins are dedicated temperature input channels. The series resistance cancellation (SRC) feature can automatically cancel out the effect of up to 1 kW of resistance in series with the remote thermal diode. The forward voltage of a diode or diode-connected transistor, operated at a constant current, exhibits a negative temperature coefficient of about -2 mV/C. Unfortunately, the absolute value of Vbe varies from device to device, and
The ADM1034 operates at three different currents to measure the change in Vbe. Figure 27 shows the input signal conditioning used to measure the output of an external temperature sensor. It also shows the external sensor as a substrate transistor, provided for temperature monitoring on some microprocessors. The external sensor could work equally well as a discrete transistor. If a discrete transistor is used, the collector is not grounded, and should be linked to the base. If a PNP transistor is used, the base is connected to the D- input and the emitter to the D+ input. If an NPN transistor is used, the emitter is connected to the D- input and the base to the D+ input. If the sensor is used in a very noisy environment, a capacitor value up to 1000 pF may be placed between the D+ and D- inputs to filter the noise. However, additional parasitic capacitance on the lines between D+, D-, and the thermal diode should also be considered. The total capacitance should never be greater than 1000 pF. To measure each DVbe, the sensor is switched between operating currents of I, (N1 x I), and (N2 x I). The resulting waveform is passed through a 65 kHz low-pass filter to remove noise, then to a chopper-stabilized amplifier that amplifies and rectifies the waveform. This produces a dc voltage proportional to DVbe. These voltage measurements determine the temperature of the thermal diode, while automatically compensating for any series resistance on the D+ and/or D- lines. The temperature is stored in two registers as a 13-bit word. To further reduce the effects of noise, digital filtering is performed by averaging the results of 16 measurement cycles at conversion rates of less than or equal to 8 Hz. An external temperature measurement takes nominally 32 ms when averaging is enabled and 6 ms when averaging is disabled. One LSB of the ADC corresponds to 0.03125C. The ADM1034 can theoretically measure temperatures from -64C to +191.96875C, although these are outside its operating range. The extended temperature resolution data format is shown in Table 5. The data for the local and remote channels is stored in the extended temperature resolution registers (Reg. 0x40 = Local, Reg. 0x42 = Remote 1, and Reg. 0x44 = Remote 2).
http://onsemi.com
14
ADM1034
Table 6. Temperature Measurement Registers
Register 0x40 0x41 0x42 0x43 0x44 0x45 Description Local Temperature, LSBs Local Temperature, MSBs Remote 1 Temperature, LSBs Remote 1 Temperature, MSBs Remote 2 Temperature, LSBs Remote 2 Temperature, MSBs Default 0x00 0x00 0x00 0x00 0x00 0x00
Table 7. Temperature Measurement Limit Registers
Register 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 Description Local High Limit Local Low Limit Local THERM Limit Remote 1 High Limit Remote 1 Low Limit Remote 1 THERM Limit Remote 2 High Limit Remote 2 Low Limit Remote 2 THERM Limit Default 0x8B (75C) 0x54 (20C) 0x95 (85C) 0x8B (75C) 0x54 (20C) 0x95 (85C) 0x8B (75C) 0x54 (20C) 0x95 (85C)
High and low temperature limit registers are associated with each temperature measurement channel. Exceeding the programmed high and low limits sets the appropriate status bit. Exceeding either limit can cause an SMBusALERT interrupt.
VDD I N2 x I N1 x I IBIAS
D+ REMOTE SENSING TRANSISTOR
VOUT+ TO ADC VOUT-
D-
LOW-PASS FILTER fC = 65kHz
Figure 27. ADM1034 Signal Conditioning Additional Functions Table 8. Channel Selector
Bits 5:4 00 01 10 11 Channel Selector (Configuration 2) Local Channel = Default Remote 1 Channel Remote 2 Channel Reserved
Several other temperature measurement functions available on the ADM1034 offer the systems designer added flexibility.
Turn-off Averaging
The ADM1034 performs averaging at conversion rates of less than or equal to 8 conversions per second. This means that the value in the measurement register is the average of 16 measurements. For faster measurements, set the conversion rate to 16 conversions per second or greater. (Averaging is not carried out at these conversion rates.) Alternatively, switch off averaging at the slower conversion rates by setting Bit 1 (AVG) of Configuration 1 Register (Address 0x01).
Single-Channel ADC Conversions
Removing Temperature Errors
In normal operating mode, the ADM1034 converts on three temperature channels: the local temperature channel, and the remote 1 and remote 2 channels. However, the user has the option to set up the ADM1034 to convert on one channel only. To enable single-channel mode, the user sets the round-robin bit (Bit 7) in Configuration Register 2 (Address 0x02) to 0. When the round-robin bit equals 1, the ADM1034 converts on all three temperature channels. In single-channel mode, it converts on one channel only, to be determined by the state of the channel selector bits (Bits 5 and 4) of the Configuration Register 2 (Address 0x02).
As CPUs run faster and faster, it gets more difficult to avoid high frequency clocks when routing the D+ and D- traces around a system board. Even when the recommended layout guidelines are followed, temperature errors attributed to noise coupled onto the D+ and D- lines remain. High frequency noise generally gives temperature measurements that are consistently too high. The ADM1034 has Local, Remote 1, and Remote 2 temperature offset registers at 0x16, 0x17, and 0x18; one for each channel. By completing a one-time calibration, the user can determine the offset caused by the system board noise and remove it using the offset registers. The registers automatically add a twos compliment word to the remote temperature measurements, ensuring correct readings in the value registers.
http://onsemi.com
15
ADM1034
Table 9. Offset Registers
Registration 0x16 0x17 0x18 Description Local Offset Remote 1 Offset Remote 2 Offset Default 0x00 0x00 0x00
Table 10. Offset Register Values
Code 0 0000 000 0 0000 001 0 0000 111 0 0001 111 0 0111 111 0 1111 111 1 0000 000 1 1111 000 Offset Value 0C (Default Value) 0.125C 0.875C 1.875C 7.875C 15.875C -16C -0.875C
temperature difference. Unless there are two thermocouples with a big temperature differential between them, the voltages should be much less than 200 mV. * Place a 0.1 mF bypass capacitor close to the ADM1034. * If the distance to the remote sensor is more than 8 inches, twisted pair cable is recommended. This works up to about 6 feet to 12 feet. * For very long distances (up to 100 feet), use shielded twisted pair such as Belden #8451 microphone cable. Connect the twisted pair to D+ and D- and the shield to GND, close to the ADM1034. Leave the remote end of the shield unconnected to avoid ground loops. Because the measurement technique uses switched current sources, excessive cable and/or filter capacitance can affect the measurement. When using long cables, the filter capacitor C1 may be reduced or removed. In any case, the total shunt capacitance should never exceed 1000 pF.
Noise Filtering
Layout Considerations Digital boards can be electrically noisy environments. Try to protect the analog inputs from noise, particularly when measuring the very small voltages from a remote diode sensor. Take the following precautions: * Place the ADM1034 as close as possible to the remote sensing diode. A distance of 4 inches to 8 inches is adequate, provided that the worst noise sources such as clock generators, data/address buses, and CRTs are avoided. * Route the D+ and D- tracks close together, in parallel, with grounded guard tracks on each side. Provide a ground plane under the tracks if possible. * Use wide tracks to minimize inductance and reduce noise pickup. At least 5 mil track width and spacing are recommended.
GND 5MIL 5MIL D+ 5MIL 5MIL D- 5MIL 5MIL GND 5MIL
For temperature sensors operating in noisy environments, common practice is to place a capacitor across the D+ and D- pins to help combat the effects of noise. However, large capacitances affect the accuracy of the temperature measurement, leading to a recommended maximum capacitor value of 1000 pF. While this capacitor reduces the noise, it does not eliminate it, making it difficult to use the sensor in a very noisy environment. The ADM1034 has a major advantage over other devices when it comes to eliminating the effects of noise on the external sensor. The series resistance cancellation feature allows a filter to be constructed between the external temperature sensor and the part. The effect of any filter resistance seen in series with the remote sensor is automatically cancelled from the temperature. The construction of a filter allows the ADM1034 and the remote temperature sensor to operate in noisy environments. Figure 29 shows a low-pass R-C-R filter with the following values: R = 100 W and C = 1 nF. This filtering reduces both common-mode noise and differential noise.
100 REMOTE TEMPERATURE SENSOR 1nF 100 D- D+
Figure 28. Arrangement of Signal Tracks
Figure 29. Filter between Remote Sensor and ADM1034
* Try to minimize the number of copper/solder joints,
because they can cause thermocouple effects. Where copper/solder joints are used, make sure that they are in both the D+ and D- paths and at the same temperature. Thermocouple effects are not a major problem because 1C corresponds to approximately 200 mV, and thermocouple voltages are approximately 3 mV/C of
Limits, Status Registers, and Interrupts High and low limits are associated with each measurement channel on the ADM1034. These can form the basis of system status monitoring. A status bit can be set for any out-of-limit condition and detected by polling the device. Alternatively, SMBusALERTs can be generated to flag a processor or microcontroller of an out-of-limit condition.
http://onsemi.com
16
ADM1034
8-Bit Limits
The following is a list of all the 8-bit limits on the ADM1034:
Table 11. Temperature Limit Registers
Register 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 Description Local High Limit Local Low Limit Local THERM Limit Remote 1 High Limit Remote 1 Low Limit Remote 1 THERM Limit Remote 2 High Limit Remote 2 Low Limit Remote 2 THERM Limit Default 0x8B (75C) 0x54 (20C) 0x95 (85C) 0x8B (75C) 0x54 (20C) 0x95 (85C) 0x8B (75C) 0x54 (20C) 0x95 (85C)
Fan TACH measurements take place in parallel and are not synchronized with the temperature measurements in any way.
Status Registers
Table 12. THERM Limit Registers
Register 0x19 Description THERM % Limit Default 0xFF default
Out-of-Limit Comparisons
The ADM1034 measures all parameters in a round-robin format and sets the appropriate status bit for out-of limit conditions. Comparisons are made differently, depending on whether the measured value is compared to a high or low limit. High Limit: Comparison Performed Low Limit: < Comparison Performed
Analog Monitoring Cycle Time
The results of limit comparisons are stored in the status registers. A 1 represents an out-of-limit measurement; a 0 represents an in-limit measurement. The status registers are located at Addresses 0x4F to 0x51. If the measurement is outside its limits, the corresponding status register bit is set to 1. It remains set at 1 until the measurement falls back within its limits and it is read or until an ARA is completed. Poll the state of the various measurements by reading the status registers over the serial bus. If Bit 0 (ALERT low) of Status Register 3 (Address 0x51) is set, this means that the ALERT output has been pulled low by the ADM1034. Pin 14 can be configured as a SMBusALERT output. This automatically notifies the system supervisor of an out-of-limit condition. Reading the status register clears the status bit as long as the error condition is gone. Status register bits are sticky. Whenever a status bit is set due to an out-of-limit condition, it remains set even after the triggering event has gone. The only way to clear the status bit is to read the status register (after the event has gone). Interrupt mask registers (Reg. 0x08, Reg. 0x09, Reg. 0x0A) allow individual interrupt sources to be masked from causing an ALERT. However, if one of these masked interrupt sources goes out of limit, its associated status bit is set in the status register.
Table 13. Interrupt Status Register 1 (Reg. 0x4F)
Bit # 7 6 5 4 3 2 1 0 Name LH LL R1H R1L R1D R2H R2L R2D Description 1 = Local high temperature limit has been exceeded. 1 = Local low temperature limit has been exceeded. 1 = Remote 1 high temperature limit has been exceeded. 1 = Remote 1 low temperature limit has been exceeded. 1 = Remote 1 diode error; indicates an open or short on the D1+/D1- pins. 1 = Remote 2 high temperature limit has been exceeded. 1 = Remote 2 low temperature limit has been exceeded. 1 = Remote 2 diode error; indicates an open or short on the D2+/D2- pins.
The analog monitoring cycle time begins on powerup, or, if monitoring has been disabled, by writing a 1 to the monitor/ STBY bit of Configuration Register 1, (Address 0x01). The ADC measures each one of the analog inputs in turn; as each measurement is completed, the result is automatically stored in the appropriate value register. The round-robin monitoring cycle continues unless it is disabled by writing a 0 to the monitor/STBY bit (Bit 0) of Configuration Register 1 (Address 0x01). The ADC performs round-robin conversions and takes 11 ms for the local temperature measurement and 32 ms for each remote temperature measurement with averaging enabled. The total monitoring cycle time for the average temperatures is therefore nominally
(2 32) ) 11 + 75 ms
(eq. 2)
Once the conversion time elapses, the round robin starts again. For more information, refer to the Conversion Rate Register section.
http://onsemi.com
17
ADM1034
Table 14. Status Register 2 (Reg. 0x50)
Bit # 7 6 5 4 3 Name LT R1T R2T T% TA Description 1 = Local THERM temperature limit has been exceeded. 1 = Remote 1 THERM temperature limit has been exceeded. 1 = Remote 2 THERM temperature limit has been exceeded. 1 = THERM % on-time limit has been exceeded. 1 = One of the THERM limits has been exceeded; and the THERM output signal has been asserted. 1 = THERM state. Indicates the THERM pin is active; clears on a read if THERM is not active. Does not generate an ALERT in ALERT comp mode. Reserved. Reserved.
the ALERT output remains low until the corresponding status register is read or until an ARA is completed (as long as no other measurement is outside its limits). For comp mode, set the ALERT configuration bit (Bit 3) of Configuration Register 1 (Address 0x01) to1. In comp mode, the ALERT output is automatically pulled low when a measurement goes outside its programmed limits. Once the measurement falls back within its limits (and assuming no other measurement channel is outside its limits), the ALERT output is automatically pulled high again. The main difference between the two modes is that the SMBusALERT does not reset without software intervention, whereas the comp mode ALERT output automatically resets.
TEMPERATURE LIMITS
2
TS
1 0
Res Res
ALERT, 70C
Table 15. Status Register 3 (Reg. 0x51)
Bit # 7 6 5 4 3 2 1 0 Name F1S FA F2S Res Res Res Res ALERT Description 1 = Fan 1 has stalled. 1 = Fan alarm speed. Fan1 and Fan 2 are running at alarm speed. 1 = Fan 2 has stalled. Reserved. Reserved. Reserved. Reserved. 1 = ALERT low; indicates the ALERT line has been pulled low.
SMBusALERT ALERT COMP CLEARED ON READ TIME
Figure 30. ALERT Comparator and SMBusALERT Outputs Handling SMBusALERT Interrupts
HIGH LIMIT
ALERT Interrupt Behavior
The ADM1034 generates an ALERT whenever an out-of-limit measurement is made (if it is not masked out). The user can also detect out-of-limit conditions by polling the ADM1034 status registers. It is important to note how the SMBus ALERT output behaves when writing interrupt handler software. The ALERT output on the ADM1034 can be programmed to operate in either SMBusALERT mode or in comp mode. In SMBusALERT mode, the ALERT output remains low until the measurement falls back within its programmed limits and either the status register is read or an ARA is completed. In comp mode, the ALERT output automatically resets once the temperature measurement falls back within the programmed limits.
Configuring the ALERT Output
TEMPERATURE CLEARED ON READ (TEMP BELOW LIMIT) TEMP BACK IN LIMIT (STATUS BIT STAYS SET) INTERRUPT MASK BIT SET INTERRUPT MASK BIT CLEARED (SMBusALERT REARMED)
"STICKY" STATUS BIT
SMBusALERT
Figure 31. Handling SMBusALERT
For SMBusALERT mode, set the ALERT configuration bit (Bit 3) of the Configuration Register 1 (Address 0x01) to 0. In SMBusALERT mode, a status bit is set when a measurement goes outside of its programmed limit. If the corresponding mask bit is not set, the ALERT output is pulled low. If the measured value falls back within the limits,
To prevent tie-ups due to service interrupts, follow these steps: 1. Detect an SMBus assertion. 2. Enter the interrupt handler. 3. Read the status register to identify the interrupt source. 4. Mask the interrupt source by setting the appropriate mask bit in the interrupt mask registers (from Reg. 0x08 to Reg. 0x0A).
http://onsemi.com
18
ADM1034
5. Take the appropriate action for a given interrupt source. 6. Exit the interrupt handler. 7. Periodically poll the status register. If the interrupt status bit clears, reset the corresponding interrupt mask bit to 0. The SMBusALERT output and status bits then behave as shown in Figure 31.
Interrupt Masking Register Table 18. Mask Register 3 (Reg. 0x0A)
Bit # 7 6 5 4 3 2 1 0 Name F1S FA F2S Res Res Res Res Res Description 1 masks the ALERT for Fan 1 stalling. 1 masks the ALERT for fans at ALARM speed. 1 masks the ALERT for Fan 2 stalling. Reserved. Reserved. Reserved. Reserved. Reserved.
Mask Registers 1, 2, and 3 are located at Addresses 0x08, 0x09, and 0x0A. These allow individual interrupt sources to be masked out to prevent the SMBusALERT interrupts. Masking the interrupt source prevents only the SMBusALERT from being asserted; the appropriate status bit is still set as normal.
Table 16. Mask Register 1 (Reg. 0x08)
Bit # 7 6 5 4 3 2 1 0 Name LH LL R1H R1L R1D R2H R2L R2D Description 1 masks the ALERT for the local high temperature. 1 masks the ALERT for the local low temperature. 1 masks the ALERT for the Remote 1 high temperature. 1 masks the ALERT for the Remote 1 low temperature. 1 masks the ALERT for the Remote 1 diode errors. 1 masks the ALERT for the Remote 2 high temperature. 1 masks the ALERT for the Remote 2 low temperature. 1 masks the ALERT for the Remote 2 diode errors.
FAN_FAULT Output
The FAN_FAULT output signals when one or both of the fans stall. Pin 8, the FAN_FAULT output, is a dual-function pin. It defaults to being a FAN_FAULT output but can be reconfigured as an analog input reference for the THERM input. To do this, set the FAN_FAULT/REF (Bit 7) in Configuration Register 4 (Address 0x04) to 1.
Fault Queue
Table 17. Mask Register 2 (Reg. 0x09)
Bit # 7 6 5 4 3 Name Res Res Res T% TA Reserved. Reserved. Reserved. 1 masks the ALERT for the THERM % on-time limit. 1 masks the ALERT for the THERM limit being exceeded and the THERM output signal being asserted. 1 masks the ALERT for the THERM state; has no effect on ALERT in ALERT comp mode. Reserved. Reserved. Description
The ADM1034 has a programmable fault queue option that lets the user program the number of out-of-limit measurements allowable before generating an ALERT. The fault queue affects only temperature measurement channels and is only operational in SMBusALERT mode. It performs some simple filtering, which is particularly useful at the higher conversion rates (16, 32, and 64 conversions/second), where averaging is not carried out. There is a queue for each of the temperature channels. If L (the number programmed to the fault queue) or more consecutive out-of-limit readings are made on the same temperature channel, the fault queue fills, and the SMBusALERT output triggers. To fill the fault queue, one needs L or more consecutive out of limits on the internal temperature channel; L or more consecutive out-of-limits on the external 1 temperature channel; or L or more consecutive out-of-limits on the external 2 temperature channel. The fault queue is independent of the state of the bits in the ALERT status registers.
Table 19. Fault Queue Address 0x06
Bits <3:0> 000X 001X 01XX 1XXX Fault Queue 1 2 3 4
2
TS
1 0
Res Res
To reset the fault queue, do one of the following: * SMBus ARA Command * Read Status Register 1 * Power-On Reset The SMBusALERT clears, even if the condition that caused the SMBusALERT remains. The SMBusALERT is reasserted if the fault queue fills up.
http://onsemi.com
19
ADM1034
Conversion Rate Register
The ADM1034 makes up to 64 measurements per second. However, for the sake of reduced power consumption and better noise immunity, users may run the ADM1034 at a slower conversion rate. Better noise immunity results from the averaging that occurs at the slower conversion rates. Averaging does not occur at rates of 16, 32, or 64 conversions per second. Table 20 lists the available conversion rates. Note that the current round-robin loop must be finished for conversion rates changes to take effect.
Table 20. Conversion Rates
Code 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B to 0xFF Conversion Rate 0.0625 0.125 0.25 0.5 1 2 4 8 16 32 64 Reserved
THERM I/O Timer and Limits
Pin 7 can be configured as either an input or output. As an output it is asserted low to signal that the measured temperature has exceeded preprogrammed temperature limits. The output is automatically pulled high again when the temperature falls below the THERM - Hys limit. The value of hysteresis is programmable in Register 0x1A. THERM is enabled as an output by default on powerup.
TEMPERATURE LIMITS THERM, 85C THERM-HYST, 80C
To configure THERM as an input, the user must set the THERM timer bit (Bit 2) of Configuration Register 1 (Address 0x01) to 1. (It no longer operates as an output.) The ADM1034 can then detect when the THERM input is asserted low. This may be connected to a trip point temperature sensor or to the FAN_FAULT PROCHOT output of a CPU. With processor core voltages reducing all the time, the threshold for the AGTL + PROCHOT output also reduces down as new processors become available. The default threshold on the input is the normal CMOS threshold. However, Pin 8 (FAN_FAULT/REF) can also be reconfigured as a REF input. This is done by setting Bit 7 (FAN_FAULT/REF) in Configuration Register 4 (Address 0x04). Connect the processor VCCP to this input to provide a reference for the THERM input. The resulting THERM threshold is 0.75xVCCP, which is the correct threshold for an AGTL+ signal. The ADM1034 also measures assertion times on the THERM input as a percentage of a time window. This time window is programmable in Configuration Register 4 (Address 0x04) by using Bits <6:4> (THERM % Time Window). Values between 0.25 seconds and 8 seconds are programmable. The assertion time as a percentage of the time window is stored in the THERM % On-Time Register (Address 0x4E). A THERM % limit is also associated with this register. Once the measured percentage exceeds the percentage limit, the THERM % Exceeded Bit (Bit 4) in Status Register 2 (Address 0x50) is asserted and an ALERT is generated, that is, if the mask bit is not set. If the limit is set to 0x00, an ALERT is generated on the first assertion. If the limit is set to 0xFF, an ALERT is never generated. This is because 0xFF corresponds to the THERM input, which is asserted continuously.
Table 21. Conversion Rates
Code 000 001 010 011 100 101 110 111 THERM % On-Time Window 0.25 s 0.5 s 1s 2s 4s 8s 8s 8s
TIME THERM
Figure 32. THERM Behavior
Once the THERM limits are exceeded, the fans are boosted to full speed, that is, as long as the Boost Disable Bit (Bit 1) is not set in Configuration Register 2 (Address 0x02).
When THERM is configured as an input only, setting the Enable THERM Events bits in Configuration Register 4 allows Pin 7 to operate as an I/O. The user can configure the THERM pin to be pulled low as an output whenever the local temperature exceeds the local THERM limit. To do this, set the Enable Local THERM events bit (Bit 0) of Configuration Register 4 (Address 0x04).
http://onsemi.com
20
ADM1034
The user can also configure the THERM pin to be pulled low as an output whenever the Remote 1 temperature exceeds the Remote 1 THERM limit. Set the Enable Remote 1 THERM events bit (Bit 1) of Configuration Register 4 (Address 0x04). The last option is to configure the THERM pin to be pulled low as an output whenever the Remote 2 temperature exceeds the Remote 2 THERM limit. Set the Enable Remote 2 THERM events bit (Bit 2) of Configuration Register 4 (Address 0x04).
THERM % Limit Register
12V 10k 10k 4.7k TACH 12V
TACH
12V FAN
1N4148
ADM1034
DRIVE
3.3V 100k
Q1 NDT3055L
The THERM % limit is programmed to Register 0x19. An ALERT is generated, if THERM is asserted for longer than the programmed percentage limit. The limit is programmed as a percentage of the chosen time window. THERM % limit register is an 8-bit register. 0x00 = 0% 0xFF = 100% Therefore, 1 LSB = 0.39%. Example: If a time window of 8 seconds is chosen, and an ALERT is to be generated if THERM is asserted for more than 1 second, program the following value to the limit register: % Limit = 1/8 x 100 = 12.5% 12.5% / 0.39% = 32d = 0x20 = 0010 0000 An ALERT is generated if the THERM limit is exceeded after the time window has elapsed, assuming it is not masked.
Fan Drive Signal
Figure 33. Interfacing a 3-Wire Fan to the ADM1034 by Using an N-Channel MOSFET
Figure 33 uses a 10 kW pullup resistor for the TACH signal. This assumes that the TACH signal is an open collector from the fan. In all cases, the fan's TACH signal must be kept below 5.0 V maximum to prevent damaging the ADM1034. If in doubt as to whether a fan has an open-collector or totem pole TACH output, use one of the input signal conditioning circuits shown in the Fan Inputs section. When designing drive circuits with transistors and FETs, make sure that the drive pins are not required to source current and that they sink less than the maximum current specified here.
Synchronous Speed Control
The ADM1034 contols the speed of up to two cooling fans. Varying the duty cycle (on/off time) of a square wave applied to the fan varies the speed of the fan. The ADM1034 uses a control method called synchronous speed control, in which the PWM drive signal applied to the fan is synchronized with the fan's TACH signal. See the Synchronous Speed Control section for more information. The external circuitry required to drive the fan is very simple. A single N-channel MOSFET is the only drive device required. The specifications of the MOSFET depend on the maximum current required by the fan and the gate voltage drive (VGS < 3.0 V for direct interfacing to the drive pin). VGS can be greater than 3.0 V, as long as the pullup on the gate is tied to 5.0 V. The MOSFET should also have a low on-resistance to ensure that there is no significant voltage drop across the FET. A high on-resistance reduces the voltage applied across the fan and therefore the maximum operating speed of the fan. Figure 33 shows a scheme for driving a 3-wire fan.
The ADM1034 drives the fan by using a control scheme called synchronous speed control. In this scheme, the PWM drive signal applied to the fan is synchronized with the TACH signal. Accurate and repeatable fan speed measurements are the main benefits. The fan is allowed to run reliably at speeds as low as 30 percent of the full capability. The drive signal applied to the fan is synchronized with the TACH signal. The ADM1034 switches on the drive signal and waits for a transition on the TACH signal. When a transition takes place on the TACH signal, the PWM drive is switched off for a period of time called toff. The drive signal is then switched on again. The toff time is varied in order to vary the fan speed. If the fan is running too fast, the toff time is increased. If the fan is running too slow, the toff time is decreased. Since the drive signal is synchronized with the TACH signal, the frequency with which the fan is driven depends on the current speed of the fan and the number of poles in it. Figure 34 shows how the synchronous speed drive signal works. The ideal TACH signal is the TACH signal that would be output from the fan if power were applied 100 percent of the time. It is representative of the actual speed of the fan. The actual TACH signal is the signal the user would see on the TACH output from the fan if the user were to put a scope on it. In effect, the actual TACH signal is the ideal TACH signal chopped with the drive signal.
http://onsemi.com
21
ADM1034
POLE TRANSITION POINTS
IDEAL TACH
tPOLE
DRIVE
tOFF
ACTUAL TACH
DASH = TACH FLOATS HIGH BY PULL-UP RESISTOR SOLID = TRUE TACH WHEN FAN IS POWERED
Figure 34. Drive Signal by Using Synchronous Control Fan Inputs
5V OR 12V FAN VCC
Pin 2 and Pin 4 are TACH inputs intended for fan speed measurement. These inputs are open-drain. Signal conditioning on the ADM1034 accommodates the slow rise and fall time of typical tachometer outputs. The maximum input signal range is from 0 V to 5.0 V, even when VCC is less than 5.0 V. In the event that these inputs are supplied from fan outputs exceeding 0 V to 5.0 V, either resistive attenuation of the fan signal or diode clamping must be used to keep the fan inputs within an acceptable range. Figure 35 to Figure 38 show examples of possible fan input circuits. If the fan TACH has a resistive pullup to VCC, it can be connected directly to the fan output.
5V OR 12V FAN VCC
PULL-UP 4.7k TYP
TACH OUTPUT VCC
ADM1034
TACH X ZD1* FAN SPEED COUNTER DRIVE X
100k TYP
*CHOOSE ZD1 VOLTAGE APPROXIMATELY 0.8 x VCC
Figure 36. Fan with TACH Pullup to Voltage > 5.0 V, Clamped with Zener Diode
PULL-UP 4.7k TYP
TACH OUTPUT VCC TACH X
ADM1034
FAN SPEED COUNTER DRIVE X
If the fan has a strong pullup (less than 1 kW to +12 V) or a totem-pole output, a series resistor can be added to limit the Zener current, as shown in Figure 37. Alternatively, a resistive attenuator may be used, as shown in Figure 38. R1 and R2 should be chosen such that
2.0 V t V PULLUP R2 (R PULLUP ) R1 ) R2) t 5.0 V
(eq. 3)
100k TYP
If the fan output has a resistive pullup to 12 V (or another voltage greater than 5.0 V), the fan output can be clamped with a Zener diode, as shown in Figure 36. The Zener voltage should be chosen so that it is greater than VIH but less than 5.0 V. Allowing for the voltage tolerance of the Zener, a value of between 3.0 V and 5.0 V is suitable.
Figure 35. Fan with TACH Pullup to +VCC
The fan inputs have an input resistance of nominally 160 kW to ground. This should be taken into account when calculating resistor values. With a pullup voltage of 12 V and pullup resistor less than 1 kW, suitable values for R1 and R2 would be 100 kW and 47 kW. This gives a high input voltage of 3.83 V.
12V VCC
ADM1034
FAN(0-7) PULL-UP TYP <1 k OR TOTEM POLE FAN SPEED COUNTER
* CHOOSE ZD1 VOLTAGE APPROXIMATELY 0.8 x V CC
Figure 37. Fan with Strong TACH. Pullup to >VCC or Totem-Pole Output, Clamped with Zener and Resistor http://onsemi.com
22
ADM1034
12V VCC
Fan Speed Measurement Registers
<1 k
ADM1034
R1* TACH OUTPUT FAN(0-7) R2 FAN SPEED COUNTER
These 16-bit measurements are stored in the TACH value registers.
Table 22. TACH Value Registers
Register 0x4A 0x4B 0x4C 0x4D Description TACH1 Period, LSB TACH1 Period, MSB TACH2 Period, LSB TACH2 Period, MSB Default 0xFF 0xFF 0xFF 0xFF
*SEE TEXT
Figure 38. Fan with Strong TACH. Pullup to >VCC or Totem-Pole Output, Attenuated with R1/R2 Fan Speed Measurement
The fan counter does not count the fan TACH output pulses directly. This is because the fan may be spinning at less than 1000 rpm and it would take several seconds to accumulate a reasonably large and accurate count. Instead, the period of the fan revolution is measured by gating an on-chip 81.92 kHz oscillator into the input of a 16-bit counter for one complete revolution of the fan. Therefore, the accumulated count is actually proportional to the fan tachometer period and inversely proportional to the fan speed. The number of poles in the fan must be programmed in Configuration Register 3 (Address 0x03). Bits <3:0> set the number of poles for Fan 1, and Bits <7:4> set the number of poles for Fan 2. This number must be an even number only, because there cannot be an uneven number of poles in a fan. A TACH period is output for every two poles. Therefore, the number of poles must be known so that the ADM1034 can measure for a full revolution. Figure 39 shows the fan speed measurement period, assuming that the fan outputs an ideal TACH signal. In reality, the TACH signal output by the fan is chopped by the drive signal. However, since the drive and the TACH signal are synchronized, there is enough information available for the ADM1034 to measure the fan speed accurately.
CLOCK
Reading Fan Speed
Reading back fan speeds involves a 2-register read for each measurement. The low byte should be read first. This freezes the high byte until both high and low byte registers have been read, preventing erroneous fan speed measurement readings. The fan tachometer reading registers report back the number of 12.2 ms period clocks (81.92 kHz oscillator) gated to the fan speed counter, for one full rotation of the fan, assuming the correct number of poles is programmed. Since the ADM1034 essentially measures the fan TACH period, the higher the count value, the slower the actual fan speed. A 16-bit fan TACH reading of 0xFFFF indicates that the fan has stalled or is running very slowly (< 75 rpm).
Calculating Fan Speed
IDEAL TACH
FAN MEASUREMENT PERIOD
Fan speed in rpm is calculated as follows. This assumes that the number of poles programmed in the Configuration Register 3 (Address 0x03) is correct for both fans. Fan Speed (RPM) = (81920 x 60)/Fan TACH Reading where: Fan TACH Reading = 16-bit Fan TACHometer Reading Example: TACH1 High Byte (Reg. 0x4A) = 0x17 TACH1 Low Byte (Reg. 0x4B) = 0xFF What is Fan 1 speed in rpm? Fan 1 TACH Reading = 0x17FF = 6143d RPM = (f x 60) / Fan 1 TACH reading RPM = (81920 x 60) / 6143 Fan Speed = 800 RPM
Alarm Speed
Figure 39. Fan Speed Measurement for a 4-Pole Fan
The fan ALARM speed (Bit 6) in Status Register 3 (Address 0x51) is set whenever the fan runs at alarm speed. This occurs if the device is programmed to run the fan at full speed whenever the THERM temperature limits are exceeded. The device runs at alarm speed, for example, if the Boost Disable bit (Bit 1) of the Configuration 2 Register (Address 0x02) is not set to 1.
http://onsemi.com
23
ADM1034
Fan Response Register Programming Target Fan Speed
The ADM1034 fan speed controller operates by reading the current fan speed, comparing it with the programmed fan speed, and then updating the drive signal applied to the fan. The rate at which the ADM1034 looks at and updates the drive signal is determined by the fan response register. Different fans have different inertias and respond to a changing drive signal more or less quickly than others. The fan response register allows the user to tailor the ADM1034 to a particular fan to prevent situations like overshoot. The user programs the number of updates the ADM1034 can make to the drive signal per second. Table 23 lists the available options.
Table 23. Fan Response Codes
Code 000 001 010 011 100 101 110 111 Update Rate 1.25 updates/second 2.5 updates/second = default 5 updates/second 10 updates/second 20 updates/second 40 updates/second 80 updates/second 160 updates/second
In this mode, the user programs the target fan speed as a TACH count for N poles or a TACH count for one full rotation of the fan, assuming the number of poles is programmed correctly in the Configuration 3 Register (Address 0x03). Use the following steps to program the target fan speed: 1. Place the ADM1034 into manual mode. Set Bit 7 (Table/SW) of Configuration Register 1 (Address 0x01) = 0. 2. Program the target TACH count (fan speed) using the following equation: TACH Count = (f x 60)/R where: f = clock frequency = 81.92 kHz R = required RPM value Example 1: If the desired speed for Fan 1 is 5000 rpm, program the following value to the TACH count registers: TACH Count = (f x 60)/5000 TACH Count = 983d = 0x03D7 Example 2: If the desired speed for Fan 2 is 3500 rpm, program the following value to the TACH pulse period registers: TACH Count = (f x 60)/3500 TACH Count = 1404d = 0x057C
Table 25. Registers to be Programmed
Fan Fan 1 Fan 1 Fan 2 Fan 2 Description Look-Up Table FS1, LSB Look-Up Table FS1, MSB Look-Up Table FS2, LSB Look-Up Table FS2, MSB Address 0x2A 0x2B 0x2C 0x2D Value 0xD7 0x03 0x7C 0x05
Table 24. Conversion Rates
Bit # 7 <6:4> 3 <2:0> Function Reserved Fan 2 Response Reserved Fan 1 Response
Look-Up Table: Modes of Operation
The ADM1034 look-up table has two different modes of operation used to determine the behavior of the system: * Manual mode * Look-up table
Manual Mode
Look-Up Table
In manual mode, the ADM1034 is under software control. The software can program the required fan speed value or the target fan speed to the ADM1034, which then outputs that fan speed.
The ADM1034 allows the user to program a temperature-to-fan speed profile. There are 24 registers in the look-up table; 8 for temperature and 16 for target fan speed (each target fan speed is two registers). In total, there are eight available points. In the default configuration, four of these are for Fan 1 and four are for Fan 2. However, it can be configured such that eight points are available and both fans run from the same table. There are two options when programming the look-up table. The ADM1034 can be programmed to make the fan speed run at discrete speeds and jump to the new fan speed once the temperature threshold is crossed. Or, it can linearly ramp the TACH count between the two temperature thresholds.
http://onsemi.com
24
ADM1034
Figure 40 and Figure 41 show what the look-up table looks like if all eight points are used on the one curve for both fans. Figure 40 shows the transfer curve when the fan is programmed to run at discrete speeds. The ADM1034 spins the fan at its new speed once a threshold is crossed.
FAN SPEED TACH COUNT 8 TACH COUNT 7 TACH COUNT 6 TACH COUNT 5 TACH COUNT 4 TACH COUNT 3 TACH COUNT 2 TACH COUNT 1 TACH COUNT 2 TO 8
knows the starting temperature, minimum speed, maximum temperature, and maximum speed), then all the user needs to program are four parameters: T1, T2, FS1, and FS2. The remainder of the look-up temperature thresholds should remain at their default values of +191C. If required, the FS3 should be programmed with the same value as FS2 to give the flat curve, if required. Or, the fan speeds can be left at the default value of 0. However, it is normal to program a THERM limit as well. Once this temperature is exceeded and the boost bit is set, the fans run to full speed. This overrides the look-up table.
FAN SPEED
T1
T2
T3
T4
T5
T6
T7
T8 TEMPERATURE
Figure 40. Programming the Look-Up Table in Discreet Fan Speeds Mode
TACH COUNT 1
Figure 41 shows the transfer curve if the Linear Fan Speeds option is chosen. At temperature T1, the fan runs at Fan Speed 1. As the temperature increases, the fan speed increases until it reaches Fan Speed 2 at T2.
FAN SPEED TACH COUNT 8 TACH COUNT 7 TACH COUNT 6 TACH COUNT 5 TACH COUNT 4 TACH COUNT 3 TACH COUNT 2 TACH COUNT 1
T1 TEMPERATURE
T2
T (3 TO 8) = C
Figure 42. Programming Two Points on the Look-Up Table Table 26. Look-Up Table Register Address
x 1 2 3 4 5 Temperature, x 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 FSx, LSB 0x2A 0x2C 0x2E 0x30 0x32 0x34 0x36 0x38 FSx, MSB 0x2B 0x2D 0x2F 0x31 0x33 0x35 0x37 0x39
T1
T2
T3
T4
T5
T6
T7
T8 TEMPERATURE
6 7 8
Figure 41. Programming the Look-Up Table in Linear Fan Speeds Mode
Once the temperature exceeds the highest temperature point in the look-up table, the fan speed remains at the highest speed until the temperature drops below the T7 temperature value. When the look-up table is split in two, the same applies. If the temperatures in T1 to T8 are not programmed in succession, the fan speed moves to the next highest programmed temperature as the temperature increases. Similarly, when the temperature decreases, it ignores programmed higher temperatures and jumps to the next lower temperature. Therefore, the temperature-to-fan speed profile for increasing and decreasing temperature can be different. When programming the look-up table, the user has the option to use between two and eight points for each fan (eight points only if the same curve is to be used for both fans). If the user just wants to program a transfer curve (and
Setting Up the Size of the Look-Up Table
When 4:8 Look-Up (Bit 3)is set to 0 (default), four points are used for each fan. When 4:8 Look-Up (Bit 3) is set to 1, all eight points on the table are used for both fans.
Setting Up the Look-Up Table in Linear Mode
When Discrete/Linear Speed (Bit 2) is set to 1 (default), the TACH count decreases linearly (and therefore the fan speed increases) with temperature. Example: At temperature TX, the fans run at FSX and fan speed increases with temperature to FSX+1 at temperature TX+1. Alternatively, the fan can be run at discrete fan speeds. When Discrete/Linear Speed (Bit 2) is set to 0, the fan runs at a new speed once the temperature threshold is exceeded.
http://onsemi.com
25
ADM1034
Setting Which Temperature Channel Controls a Fan
Fan Behavior Register (Address 0x07) Bits <1:0> = DRIVE1 Behavior (D1B) Bits <3:2> = DRIVE2 Behavior (D2B) The ADM1034 can be configured so that Fan 1 or Fan 2 can be controlled by either the local temperature, or by the Remote 1 or Remote 2 temperatures.
Table 27. Drive X BHVR Bits
Bits 00 01 10 11 DRIVE x BHVR Local Temperature Controls Fan x Remote 1 Temperature Controls Fan x Remote 2 Temperature Controls Fan x Fan x Runs at Full Speed
Programming the THERM Limit for Each Temperature Channel
By default, Remote 1 controls Fan 1, and Remote 2 controls Fan 2. If the ADM1034 is in single-channel mode and one of the fans is set up to run from a temperature channel that is not being measured, the drive X BHVR bits are set to 11 and the fan is run at full speed.
Look-Up Table Hysteresis
THERM is the absolute maximum temperature allowed on a temperature channel. Above this temperature, a component such as the CPU or VRM may be operating beyond its safe operating limit. When the temperature measured exceeds THERM, all fans are driven at full speed to provide critical system cooling. The fans remain running at full speed until the temperature drops below THERM - Hysteresis. The hysteresis value is programmable; its default is 5C. If the Boost Disable bit (Bit 1) is set in Configuration Register 2, the fans do not run to full speed. The THERM limit is considered the maximum worst-case operating temperature of the system. Exceeding any THERM limit runs all fans at full speed, a condition with very negative acoustic effects. This limit should be set up as a fail-safe and not exceeded under normal system operating conditions. The THERM temperature limit registers are listed in Table 29.
Table 29. THERM Hysteresis Registers
Address 0x0D 0x10 0x13 Description Local THERM Limit Remote 1 THERM Limit Remote 2 THERM Limit Default 0x95 (85C) 0x95 (85C) 0x95 (85C)
The user can program a hysteresis to be applied to the look-up table. The advantage of this is apparent if the temperature is cycling around one of the threshold temperatures and causing the fan speed to switch between the two speeds, particularly when the look-up table is configured in discrete mode. It would not be as important in the linear mode.
Programming the Look-Up Table Hysteresis
The look-up table's hysteresis register is at Address 0x3A. A hysteresis value of between 0C and 15C can be programmed with a resolution of 1C and applied to all the temperature thresholds. Table 28 gives examples of values for programming.
Table 28. Programming the Hysteresis
Code 0000 0000 0000 0001 0000 0010 0000 0101 0000 1000 0000 1111 Hysteresis Value 0C 1C 2C 5C = Default 8C 15C
The THERM hysteresis register is at Address 0x1A. A hysteresis value is programmed and applied to all three temperature channels; Local, Remote 1, and Remote 2. A THERM hysteresis value of between 0C and 15C can be programmed with a resolution of 1C. Table 33 gives some examples.
Table 30. Programming THERM Hysteresis
Code 0000 0000 0000 0001 0000 0010 0000 0101 0000 1000 0000 1111 Hysteresis Value 0C 1C 2C 5C = Default 8C 15C
http://onsemi.com
26
ADM1034
XOR Tree Test Mode Lock Bit
The ADM1034 includes an XOR tree test mode. This is useful for in circuit test equipment at board level testing. By applying stimulus to the pins included in the XOR test, it is possible to detect opens or shorts on the system board. Figure 43 shows the signals that are exercised in the XOR tree test mode. The XOR tree test is enabled by setting the XOR bit (Bit 3) in Configuration 4 Register (0x04).
TACH1 DRIVE2
Setting the Lock bit (Bit 6) of Configuration Register 1 (Address 0x01) makes all the lockable registers read-only. These registers remain read-only until the ADM1034 is powered down and back up again. For more information on which registers are lockable, see Table 31.
SW Reset
Setting the Software Reset bit (Bit 0) of Configuration Register 2 (Address 0x02) resets all software resettable bits to their default value. For more information on resetting registers and their default values, see Table 31 to Table 71.
THERM
FAN_FAULT/REF
LOCATION
ALERT
DRIVE1
Figure 43. XOR Tree Test Table 31. ADM1034 Registers
Address 0x00/80 0x01/81 0x02/82 0x03/83 0x04/84 0x05/85 0x06/86 0x07/87 0x08/88 0x09/89 0x0A/8A 0x0B/8B 0x0C/8C 0x0D/8D 0x0E/8E 0x0F/8F R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description #Bytes/Block Read Configuration 1 Configuration 2 Configuration 3 Configuration 4 Conversion Rate Fault Queue Fan Behavior Mask 1 Mask 2 Mask 3 Local High Limit Local Low Limit Local THERM Limit Remote 1 High Limit Remote 1 Low Limit Bit 7 7 Table /SW RR #FP2 FF/ REF RES RES F2 Off LH RES F1S 7 7 7 7 7 Bit 6 6 Lock RES #FP2 %T RES RES F1 Off LL RES FA 6 6 6 6 6 Bit 5 5 SDA CS #FP2 %T RES RES RES R1H RES F2S 5 5 5 5 5 Bit 4 4 SCL CS #FP2 %T RES RES RES R1L %T RES 4 4 4 4 4 Bit 3 3 ALERT LUT #FP1 XOR Conv FQ D2B R1D TA RES 3 3 3 3 3 Bit 2 2 TIMER D/L #FP1 R2TM Conv FQ D2B R2H TS RES 2 2 2 2 2 Bit 1 1 Avg BD #FP1 R1TM Conv FQ D1B R2L RES RES 1 1 1 1 1 Bit 0 0 Mon Reset #FP1 LTM Conv FQ D1B R2D RES RES 0 0 0 0 0 Default 0x20 0x01 0x84 0x44 0x00 0x07 0x01 0x09 0x52 0x18 0x00 0x8B 0x54 0x95 0x8B 0x54 Lock- able? Y Y Y Y Y Y Y Y N N N N N Y N N
http://onsemi.com
27
ADM1034
Table 31. ADM1034 Registers
Address 0x10/90 0x11/91 0x12/92 0x13/93 0x16/96 0x17/97 0x18/98 0x19/99 0x1A/9A 0x22/A2 0x23/A3 0x24/A4 0x25/A5 0x26/A6 0x27/A7 0x28/A8 0x29/A9 0x2A/AA 0x2B/AB 0x2C/AC 0x2D/AD 0x2E/AE 0x2F/AF 0x30/B0 0x31/B1 0x32/B2 0x33/B3 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Remote 1 THERM Limit Remote 2 High Limit Remote 2 Low Limit Remote 2 THERM Limit Local Offset Remote 1 Offset Remote 2 Offset THERM % Limit THERM Hysteresis Look-Up Table T1 Look-Up Table T2 Look-Up Table T3 Look-Up Table T4 Look-Up Table T5 Look-Up Table T6 Look-Up Table T7 Look-Up Table T8 Look-Up Table, FS1 Look-Up Table, FS1 Look-Up Table, FS2 Look-Up Table, FS2 Look-Up Table, FS3 Look-Up Table, FS3 Look-Up Table, FS4 Look-Up Table, FS4 Look-Up Table, FS5 Look-Up Table, FS5 Bit 7 7 7 7 7 7 7 7 7 RES 7 7 7 7 7 7 7 7 7 15 7 15 7 15 7 15 7 15 Bit 6 6 6 6 6 6 6 6 6 RES 6 6 6 6 6 6 6 6 6 14 6 14 6 14 6 14 6 14 Bit 5 5 5 5 5 5 5 5 5 RES 5 5 5 5 5 5 5 5 5 13 5 13 5 13 5 13 5 13 Bit 4 4 4 4 4 4 4 4 4 RES 4 4 4 4 4 4 4 4 4 12 4 12 4 12 4 12 4 12 Bit 3 3 3 3 3 3 3 3 3 Hys 3 3 3 3 3 3 3 3 3 11 3 11 3 11 3 11 3 11 Bit 2 2 2 2 2 2 2 2 2 Hys 2 2 2 2 2 2 2 2 2 10 2 10 2 10 2 10 2 10 Bit 1 1 1 1 1 1 1 1 1 Hys 1 1 1 1 1 1 1 1 1 9 1 9 1 9 1 9 1 9 Bit 0 0 0 0 0 0 0 0 0 Hys 0 0 0 0 0 0 0 0 0 8 0 8 0 8 0 8 0 8 Default 0x95 0x8B 0x54 0x95 0x00 0x00 0x00 0xFF 0x05 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF Lock- able? Y N N Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y
http://onsemi.com
28
ADM1034
Table 31. ADM1034 Registers
Address 0x34/B4 0x35/B5 0x36/B6 0x37/B7 0x38/B8 0x39/B9 0x3A/BA R/W R/W R/W R/W R/W R/W R/W R/W Description Look-Up Table, FS6 Look-Up Table, FS6 Look-Up Table, FS7 Look-Up Table, FS7 Look-Up Table, FS8 Look-Up Table, FS8 Look-Up Table Hysteresis Fan Response Device ID Company ID Revision Register Local Temperature Local Temperature Remote 1 Temperature Remote 1 Temperature Remote 2 Temperature Remote 2 Temperature TACH1 Period TACH1 Period TACH2 Period TACH2 Period THERM % Ontime Status 1 Status 2 Status 3 Bit 7 7 15 7 15 7 15 RES Bit 6 6 14 6 14 6 14 RES Bit 5 5 13 5 13 5 13 RES Bit 4 4 12 4 12 4 12 RES Bit 3 3 11 3 11 3 11 Hys Bit 2 2 10 2 10 2 10 Hys Bit 1 1 9 1 9 1 9 Hys Bit 0 0 8 0 8 0 8 Hys Default 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0x05 Lock- able? Y Y Y Y Y Y Y
0x3C/BC 0x3D/BD 0x3E/BE 0x3F/BF 0x40/C0 0x41/C1 0x42/C2 0x43/C3 0x44/C4 0x45/C5 0x4A/CA 0x4B/CB 0x4C/CC 0x4D/CD 0x4E/CE 0x4F/CF 0x50/D0 0x51/D1
R/W R R R R R R R R R R R R R R R R R
RES 7 7 7 4 12 4 12 4 12 7 15 7 15 7 LH LT F1S
F2 6 6 6 3 11 3 11 3 11 6 14 6 14 6 LL R1T FA
F2 5 5 5 2 10 2 10 2 10 5 13 5 13 5 R1H R2T F2S
F2 4 4 4 1 9 1 9 1 9 4 12 4 12 4 R1L %T RES
RES 3 3 3 0 8 0 8 0 8 3 11 3 11 3 R1D TA RES
F1 2 2 2 RES 7 RES 7 RES 7 2 10 2 10 2 R2H TS RES
F1 1 1 1 RES 6 RES 6 RES 6 1 9 1 9 1 R2L RES RES
F1 0 0 0 RES 5 RES 5 RES 5 0 8 0 8 0 R2D RES ALERT
0x11 0x34 0x41 0x02 0x00 0x00 0x00 0x00 0x00 0x00 0xFF 0xFF 0xFF 0xFF 0x00 0x00 0x00 0x00
Y N N N N N N N N N N N N N N N N N
http://onsemi.com
29
ADM1034
Table 32. Register 0x00, # Bytes/Block Read, POR = 0x20, Lock = Y, S/W Reset = Y
Bit <7:0> Name # Bytes Block Read R/W R/W Description Block reads are # bytes/block read long. The maximum is 32 bytes, the SMBus transaction limit.
Table 33. Register 0x01, Configuration Register 1, Power-On Default 0x01, Lock = Y, S/W Reset = Y
Bit 7 6 5 4 3 2 1 Name Table/SW Con Lock Bit SDA Timeout SCL Timeout ALERT Configuration Enable THERM Timer Averaging Off R/W R/W R/W R/W R/W R/W R/W R/W Description Set this bit to 1 to place the fan speed under the control of the look-up table. When this bit is 0, the ADM1034 is in software/manual control mode. Default = 0. Set this bit to 1 to prevent the user from writing to the ADM1034 registers. 1 = ADM1034 registers locked. 0 = ADM1034 registers unlocked. Default = 0. 1 = SDA timeout enabled. 0 = SDA timeout disabled. Default = 0. 1 = SCL timeout enabled. 0 = SDL timeout disabled. Default = 0. 0 = SMBusALERT. Default = 0. 1 = ALERT_COMP mode. 1 = timer enabled, 0 = timer disabled. This bit enables THERM as an input. Default = 0. This bit is used to disable averaging at the slower conversion rates (8 Hz and slower). Averaging is automatically disabled at the higher (16, 32, and 64 Hz ) conversion rates. Default = averaging on = 0. Set bit to 1 to enable temperature monitoring. Set bit to 0 to disable it. Power-On Default = 1
0
Monitor/STBY
R/W
Table 34. Register 0x02, Configuration Register 2, Power-On Default 0x84, Lock = Y, S/W Reset = Y
Bit 7 Name Round Robin R/W R/W Description This bit enables the round-robin mode. Set this bit to 0 to put the ADM1034 in single-channel mode. The ADC converts on one channel only, which is determined by the channel selector bits. Default = Round Robin = 1. Reserved. This bit determines the channel on which the ADC converts. 00 = Local Channel Only 01 = Remote 1 Channel Only 10 = Remote 2 Channel Only 11 = Reserved This bit determines how many table points are used to control each fan. 0 = 4 table points for each fan. 1 = all 8 points on one table; this table is used to control both fans. This bit determines whether the fans run at discrete speeds or at speeds that increase with temperature between the two thresholds. Default = 1 = Linear. Set bit to 1 to prevent the fans from being boosted if either THERM temperature or THERM timer limits are exceeded. Under these conditions, the fan runs at the previously calculated speed. Default = 0. Set this bit to 1 to reset the ADM1034 registers to their default values, excluding the limit registers, offset registers, and look-up table registers. This bit self-clears. Default = 0.
6 <5:4>
Reserved Channel Selector
R/W R/W
3
4:8 Look-Up Table
R/W
2 1
Discrete/Linear Speed Boost Disable
R/W R/W
0
SW Reset
R/W
Table 35. Register 0x03, Configuration Register 3, Power-On Default 0x44, Lock = Y, S/W Reset = Y
Bit <7:4> Name #Poles Fan 2 R/W R/W Description Write the number of poles on Fan 2 to this register. power-on default = 4 poles = 100. This should always be an even number, because there cannot be an odd number of poles in a fan. Write the number of poles in Fan 1 to this register. power-on default = 4 poles = 100. This should always be an even number, because there cannot be an odd number of poles in a fan.
<3:0>
#Poles Fan 1 1
R/W
http://onsemi.com
30
ADM1034
Table 36. Register 0x04, Configuration Register 4, Power-On Default 0x00, Lock = Y, S/W Reset = Y
Bit 7 <6:4> Name FAN_FAULT/REF THERM % Time Window R/W R/W R/W Description This bit sets the function for Pin 8. 0 = Default = FAN_FAULT output (THERM input is CMOS). 1 = Reference input for THERM. These bits set the time window over which THERM % is calculated. 000 = 0.25 second 001 = 0.5 second 010 = 1 second 011 = 2 seconds 100 = 4 seconds 101 = 8 seconds 110 = 8 seconds 111 = 8 seconds 3 2 1 0 XOR Test Enable Remote 2 THERM Events Enable Remote 1 THERM Events Enable Local THERM Events R/W R/W R/W R/W Set this bit to 1 to enable the XOR connectivity test. This bit enables THERM assertions as an output. Functions when the THERM timer is enabled and the Remote 2 temperature exceeeds its THERM limit. This bit enables THERM assertions as an output. Functions when the THERM timer is enabled and the Remote 1 temperature exceeeds its THERM limit. This bit enables THERM assertions as an output. Functions when the THERM timer is enabled and the local temperature exceeeds its THERM limit.
Table 37. Register 0x05, Configuration Rate Register, Power-On Default 0x07, Lock = Y, S/W Reset = Y
Bit 7 <6:4> <3:0> Res Res Conversion Rate Name R/W R R R/W Reserved. These four bits set the conversion rate of the ADM1034. Changing these bits does not update the conversion rate until the start of the next round robin. 0000 = 0.0625 conversions/second 0001 = 0.125 conversions/second 0010 = 0.25 conversions/second 0011 = 0.5 conversions/second 0100 = 1 conversion/second 0101 = 2 conversions/second 0110 = 4 conversions/second 0111 = 8 conversions/second = default 1000 = 16 conversions/second 1001 = 32 conversions/second 1010 = 64 conversions/second Description This bit is reserved for future use. Do not write to this bit.
Table 38. Register 0x06, Fault Queue, Power-On Default 0x01, Lock = Y, S/W Reset = Y
Bit <7:4> <3:0> Unused Fault Queue Length Name R/W R R/W Reserved. These four bits set the fault queue (the number of out-of-limit measurements made before an ALERT is generated). 000x = 1 001x = 2 01xx = 3 1xxx = 4 Description
http://onsemi.com
31
ADM1034
Table 39. Register 0x07, Fan Behavior Register, Power-On Default 0x09, Lock = Y, S/W Reset = Y
Bit 7 6 5 4 <3:2> Name Fan 2 Off Fan 1 Off Res Res DRIVE2 BHVR R/W R/W R/W R R R/W Set this bit to 1 to switch off Fan 2. Set this bit to 1 to switch off Fan 1. Reserved. Reserved. These bits determine which temperature source controls the DRIVE2 output. 00 = Local temperature controls DRIVE2. 01 = Remote 1 temperature controls DRIVE2. 10 = Remote 2 temperature controls DRIVE2. 11 = DRIVE2 full speed. <1:0> DRIVE1 BHVR R/W These bits determine which temperature source controls the DRIVE1 output. 00 = Local temperature controls DRIVE1. 01 = Remote 1 temperature controls DRIVE1. 10 = Remote 2 temperature controls DRIVE1. 11 = DRIVE1 full speed. Description
Table 40. Register 0x08, Mask Register 1, Power-On Default 0x52, Lock = N, S/W Reset = Y
Bit 7 6 5 4 3 2 1 0 Name Local High Local Low Remote 1 High Remote 1 Low Remote 1 Diode Error Remote 2 High Remote 2 Low Remote 2 Diode Error R/W R/W R/W R/W R/W R/W R/W R/W R/W Description A 1 disables the corresponding interrupt status bit from causing the interrupt output to be set. The status bit is not affected. Default = 0. A 1 disables the corresponding interrupt status bit from causing the interrupt output to be set. The status bit is not affected. Default = 1. A 1 disables the corresponding interrupt status bit from causing the interrupt output to be set. The status bit is not affected. Default = 0. A 1 disables the corresponding interrupt status bit from causing the interrupt output to be set. The status bit is not affected. Default = 1. A 1 disables the corresponding interrupt status bit from causing the interrupt output to be set. The status bit is not affected. Default = 0. A 1 disables the corresponding interrupt status bit from causing the interrupt output to be set. The status bit is not affected. Default = 0. A 1 disables the corresponding interrupt status bit from causing the interrupt output to be set. The status bit is not affected. Default = 1. A 1 disables the corresponding interrupt status bit from causing the interrupt output to be set. The status bit is not affected. Default = 0.
Table 41. Register 0x09, Mask Register 2, Power-On Default 0x18, Lock = N, S/W Reset = Y
Bit <7:5> 4 3 2 Unused THERM % THERM Assert THERM_State Name R/W R R/W R/W R/W Unused. A 1 disables the corresponding interrupt status bit, preventing it from causing the interrupt output. The status bit is not affected. Default = 1. A 1 disables the corresponding interrupt status bit, preventing it from causing the interrupt output. The status bit is not affected. Default = 0. A 1 disables the corresponding interrupt status bit, preventing it from causing the interrupt output. The status bit is not affected. Default = 0. This bit has no effect in ALERT comparator mode, because the corresponding status bit does not generate an ALERT in that mode. Unused. Description
<1:0>
Unused
R
http://onsemi.com
32
ADM1034
Table 42. Register 0x0A, Mask Register 3, Power-On Default 0x00, Lock = N, S/W Reset = Y
Bit 7 6 5 4 3 2 1 0 Name Fan 1 Stalled Fan Alarm Speed Fan 2 Stalled Reserved Reserved Reserved Reserved Reserved R/W R/W R/W R/W R R R R R Description A 1 disables the corresponding interrupt status bit, preventing it from causing the interrupt output. The status bit is not affected. Default = 0. A 1 disables the corresponding interrupt status bit, preventing it from causing the interrupt output. The status bit is not affected. Default = 0. A 1 disables the corresponding interrupt status bit, preventing it from causing the interrupt output. The status bit is not affected. Default = 0. Reserved. Default = 0. Reserved. Default = 0. Reserved. Default = 0. Reserved. Default = 0. Reserved. Default = 0.
Table 43. Register 0x0B, Local High Limit, Power-On Default 0x8B, Lock = N, S/W Reset = N
Bit <7:0> Name Local High Limit R/W R/W Description When the local temperature exceeds this temperature, the corresponding interrupt status bit is set.
Table 44. Register 0x0C, Local Low Limit, Power-On Default 0x54, Lock = N, S/W Reset = N
Bit <7:0> Name Local Low Limit R/W R/W Description When the local temperature falls below this temperature, the corresponding interrupt status bit is set.
Table 45. Register 0x0D, Local THERM Limit, Power-On Default 0x95, Lock = Y, S/W Reset = Y
Bit <7:0> Name Local THERM Limit R/W R/W Description When the local temperature exceeds this temperature, the corresponding status bit is set and the THERM output is activated.
Table 46. Register 0x0E, Remote 1 High Limit, Power-On Default 0x8B, Lock = N, S/W Reset = N
Bit <7:0> Name Remote 1 High Limit R/W R/W Description When the Remote 1 temperature exceeds this temperature, the corresponding interrupt status bit is set.
Table 47. Register 0x0F, Remote 1 Low Limit, Power-On Default 0x54, Lock = N, S/W Reset = N
Bit <7:0> Name Remote 1 Low Limit R/W R/W Description When the Remote 1 temperature falls below this temperature, the corresponding interrupt status bit is set.
Table 48. Register 0x10, Remote 1 THERM Limit, Power-On Default 0x95, Lock = Y, S/W Reset = N
Bit <7:0> Name Remote 1 THERM Limit R/W R/W Description When the Remote 1 temperature exceeds this temperature, the corresponding status bit is set and the THERM output is activated.
Table 49. Register 0x11, Remote 2 High Limit, Power-On Default 0x8B, Lock = N, S/W Reset = N
Bit <7:0> Name Remote 2 High Limit R/W R/W Description When the Remote 2 temperature exceeds this temperature, the corresponding interrupt status bit is set.
http://onsemi.com
33
ADM1034
Table 50. Register 0x12, Remote 2 Low Limit, Power-On Default 0x54, Lock = N, S/W Reset = N
Bit <7:0> Name Remote 2 Low Limit R/W R/W Description When the Remote 2 temperature falls below this temperature, the corresponding interrupt status bit is set.
Table 51. Register 0x13, Remote 2 THERM Limit, Power-On Default 0x95, Lock = Y, S/W Reset = N
Bit <7:0> Name Remote 2 THERM Limit R/W R/W Description When the Remote 2 temperature exceeds this temperature, the corresponding status bit is set and the THERM output is activated.
Table 52. Register 0x16, Local Offset Register, Power-On Default 0x00, Lock = Y, S/W Reset = N
Bit <7:0> Name Local Offset R/W R/W Description Allows a twos compliment offset to be automatically added to or subtracted from the local temperature measurement. Resolution = 0.125C. Maximum offset from -16C to +15.875C. Default = 0.
Table 53. Register 0x17, Remote 1 Offset Register, Power-On Default 0x00, Lock = Y, S/W Reset = N
Bit <7:0> Name Remote 1 Offset R/W R/W Description Allows a twos compliment offset to be automatically added to or subtracted from the Remote 1 temperature measurement. Resolution = 0.125C. Maximum offset from -16C to +15.875C. Default = 0.
Table 54. Register 0x18, Remote 2 Offset Register, Power-On Default 0x00, Lock = Y, S/W Reset = N
Bit <7:0> Name Remote 2 Offset R/W R/W Description Allows a twos compliment offset to be automatically added to or subtracted from the Remote 2 temperature measurement. Resolution = 0.125C. Maximum offset from -16C to +15.875C. Default = 0.
Table 55. Register 0x19, THERM Timer % Limit, Power-On Default 0xFF, Lock = Y, S/W Reset = N
Bit <7:0> Name THERM Timer on% Limit R/W R/W Description If the THERM is asserted for greater than this limit on the time window, the corresponding status bit is set.
Table 56. Register 0x1A, THERM Hysteresis, Power-On Default 0x05, Lock = Y, S/W Reset = N
Bit <7:4> <3:0> Name Reserved THERM Hysteresis R/W R R/W Reserved. An unsigned THERM hysteresis value, LSB = 1C. Once THERM has been activated on a temperature channel, the THERM limit - hysteresis is deactivated if the temperature drops below THERM. Description
http://onsemi.com
34
ADM1034
Table 57. Look-Up Table Registers, Lock = Y, S/W Reset = Y
Register Address 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Look-Up Table, T1 Look-Up Table, T2 Look-Up Table, T3 Look-Up Table, T4 Look-Up Table, T5 Look-Up Table, T6 Look-Up Table, T7 Look-Up Table, T8 Look-Up Table, FS1, LSB Look-Up Table, FS1, MSB Look-Up Table, FS2, LSB Look-Up Table, FS2, MSB Look-Up Table, FS3, LSB Look-Up Table, FS3, MSB Look-Up Table, FS4, LSB Look-Up Table, FS4, MSB Look-Up Table, FS5, LSB Look-Up Table, FS5, MSB Look-Up Table, FS6, LSB Look-Up Table, FS6, MSB Look-Up Table, FS7, LSB Look-Up Table, FS7, MSB Look-Up Table, FS8, LSB Look-Up Table, FS8, MSB Power-On Default 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF
Table 58. Register 0x3A, Look-Up Table Hysteresis, Power-On Default 0x05, Lock = Y, S/W Reset = Y
Bit <7:4> <3:0> Reserved Look-up Table Hysteresis Name R/W R R/W Reserved. These bits determine the hysteresis applied to the temperature thresholds in the look-up table. LSB size = 1C. Description
http://onsemi.com
35
ADM1034
Table 59. Register 0x3C, Fan Response Register, Power-On Default 0x11, Lock = Y, S/W Reset = Y
Bit 7 <6:4> Res Fan 2 Response Name R/W R R/W Reserved. These bits set the fan's response in the fan speed control mode. 000 = 1.25 updates/second 001 = 2.5 updates/second = Default 010 = 5 updates/second 011 = 10 updates/second 100 = 20 updates/second 101 = 40 updates/second 110 = 80 updates/second 111 = 160 updates/second 3 <2:0> Res Fan 1 Response R R/W Reserved. These bits set the fan's response in the fan speed control mode. 000 = 1.25 updates/second 001 = 2.5 updates/second = Default 010 = 5 updates/second 011 = 10 updates/second 100 = 20 updates/second 101 = 40 updates/second 110 = 80 updates/second 111 = 160 updates/second Description
Table 60. Register 0x3D, Device ID, Power-On Default 0x34, Lock = N, S/W Reset = N
Bit <7:0> Name Device ID R/W R Description This read-only value contains the device ID, which is 0x34.
Table 61. Register 0x3E, Company ID, Power-On Default 0x41, Lock = N, S/W Reset = N
Bit <7:0> Name Company ID R/W R Description This read-only value contains the company ID, which is 0x41.
Table 62. Register 0x3F, Revision Register, Power-On Default 0x02, Lock = N, S/W Reset = N
Bit <7:0> Name Revision ID R/W R Description This read-only value contains the revision ID.
Table 63. Register 0x40/41, Local Temp Registers, Power-On Default 0x00, Lock = N, S/W Reset = Y
Bit <4:0> <12:5> Name Local Temperature LSB Local Temperature MSB R/W R R Description This register contains the LSBs of the last measured local temperature value. Resolution = 0.03125C. This register contains the MSBs of the last measured local temperature value. Resolution = 1C.
http://onsemi.com
36
ADM1034
Table 64. Register 0x42/43, Remote 1 Temp Registers, Power-On Default 0x00, Lock = N, S/W Reset = Y
Bit <4:0> <12:5> Name Remote 1 Temperature LSB Remote 1 Temperature MSB R/W R R Description This register contains the LSBs of the last measured Remote 1 temperature value. Resolution = 0.03125C. This register contains the LSBs of the last measured Remote 1 temperature value. Resolution = 1C.
Table 65. Register 0x44/45, Remote 2 Temp Registers, Power-On Default 0x00, Lock = N, S/W Reset = Y
Bit <4:0> <12:5> Name Remote 2 Temperature LSB Remote 2 Temperature MSB R/W R R Description This register contains the LSBs of the last measured Remote 2 temperature value. Resolution = 0.03125C. This register contains the MSBs of the last measured Remote 2 temperature value. Resolution = 1C.
Table 66. Register 0x4A/4B, TACH1 Period, Power-On Default 0xFF, Lock = N, S/W Reset = Y
Bit <7:0> <15:8> Name Fan 1 Period Count, LSB Fan 1 Period Count, MSB R/W R R Description This register contains the LSBs of the last measured Fan 1 revolution count. This register contains the MSBs of the last measured Fan 1 revolution count.
Table 67. Register 0x4C/4D, TACH2 Period, Power-On Default 0xFF, Lock = N, S/W Reset = Y
Bit <7:0> <15:8> Name Fan 2 Period Count, LSB Fan 2 Period Count, MSB R/W R R Description This register contains the LSBs of the last measured Fan 2 revolution count. This register contains the MSBs of the last measured Fan 2 revolution count.
Table 68. Register 0x4E, THERM % On-Time, Power-On Default 0x00, Lock = N, S/W Reset = Y
Bit <7:0> Name THERM % On-Time R/W R Description Represents the % time of THERM activity within the time window set by the configuration bits.
Table 69. Register 0x4F, Status 1, Power-On Default 0x00, Lock = N, S/W Reset = Y
Bit 7 6 5 4 3 2 1 0 Name Local Temp High Local Temp Low Remote 1 Temp High Remote 1 Temp Low Remote 1 Diode Error Remote 2 Temp High Remote 2 Temp Low Remote 2 Diode Error R/W R R R R R R R R Description A 1 indicates that the local high limit has been tripped. A 1 indicates that the local low limit has been tripped. A 1 indicates that the Remote 1 high limit has been tripped. A 1 indicates that the Remote 1 low limit has been tripped. A 1 indicates that a short or an open has been detected on the Remote 1 temperature channel. This test is completed once on each conversion. A 1 indicates that the Remote 2 high limit has been tripped. A 1 indicates that the Remote 2 low limit has been tripped. A 1 indicates that a short or an open has been detected on the Remote 2 temperature channel. This test is completed once on each conversion.
http://onsemi.com
37
ADM1034
Table 70. Register 0x50, Status 2, Power-On Default 0x00, Lock = N, S/W Reset = Y
Bit 7 6 5 4 Name Local THERM Remote 1 THERM Remote 2 THERM THERM % Exceeded R/W R R R R Description A 1 indicates that the local THERM limit has been tripped. A 1 indicates that the Remote 1 THERM limit has been tripped. A 1 indicates that the Remote 2 THERM limit has been tripped. A 1 indicates that the THERM signal has been asserted for longer than the programmed limit. Clear on Read. If THERM % Limit = 0x00 and THERM is asserted, it is reasserted immediately. A 1 indicates that the THERM signal has been asserted low as an input only. A 1 indicates that the THERM pin has been asserted low as an output. Reserved. Reserved.
3 2 1 0
THERM Asserted THERM_State Reserved Reserved
R R R R
Table 71. Register 0x51, Status Register 3, Power-On Default 0x00, Lock = N, S/W Reset = Y
Bit 7 6 5 4 3 2 1 0 Name Fan 1 Stalled Fan Alarm Speed Fan 2 Stalled Reserved Reserved Reserved Reserved ALERT Low R/W R R R R R R R R A 1 indicates that Fan 1 has stalled. A 1 indicates that the fans are running at full speed due to an alarm condition, for instance, when a THERM temperature limit is exceeded. A 1 indicates that Fan 2 has stalled. Reserved. Reserved. Reserved. Reserved. A 1 indicates that the ADM1034 has pulled the ALERT output pin low. This allows polling of a single status register to determine if an ALERT condition in any of the status registers has occurred. Description
ORDERING INFORMATION
Device Number ADM1034ARQZ ADM1034ARQZ-REEL Temperature Range -40C to +125C -40C to +125C Package Type 16-Lead QSOP 16-Lead QSOP Package Option RQ-16 RQ-16 Shipping 98 Tube 2500 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *The "Z'' suffix indicates Pb-Free part.
http://onsemi.com
38
ADM1034
PACKAGE DIMENSIONS
QSOP16 CASE 492-01 ISSUE O
-A- R
Q H x 45_ U
RAD. 0.013 X 0.005 DP. MAX
-B-
MOLD PIN MARK
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. THE BOTTOM PACKAGE SHALL BE BIGGER THAN THE TOP PACKAGE BY 4 MILS (NOTE: LEAD SIDE ONLY). BOTTOM PACKAGE DIMENSION SHALL FOLLOW THE DIMENSION STATED IN THIS DRAWING. 4. PLASTIC DIMENSIONS DOES NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 6 MILS PER SIDE. 5. BOTTOM EJECTOR PIN WILL INCLUDE THE COUNTRY OF ORIGIN (COO) AND MOLD CAVITY I.D. INCHES DIM MIN MAX A 0.189 0.196 B 0.150 0.157 C 0.061 0.068 D 0.008 0.012 F 0.016 0.035 G 0.025 BSC H 0.008 0.018 J 0.0098 0.0075 K 0.004 0.010 L 0.230 0.244 M 0_ 8_ N 0_ 7_ P 0.007 0.011 Q 0.020 DIA R 0.025 0.035 U 0.025 0.035 8_ V 0_ MILLIMETERS MIN MAX 4.80 4.98 3.81 3.99 1.55 1.73 0.20 0.31 0.41 0.89 0.64 BSC 0.20 0.46 0.249 0.191 0.10 0.25 5.84 6.20 0_ 8_ 0_ 7_ 0.18 0.28 0.51 DIA 0.64 0.89 0.64 0.89 0_ 8_
RAD. 0.005-0.010 TYP
L 0.25 (0.010)
M
G T P DETAIL E
C
K -T-
SEATING PLANE M
V N 8 PL
D 16 PL 0.25 (0.010) TB
S
A
S
M
J
F DETAIL E
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
http://onsemi.com
39
ADM1034/D

▲Up To Search▲

Price & Availability of ADM1034ARQZ-REEL

	To Download ADM1034ARQZ-REEL Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .